research-article

In-situ characterization and extraction of SRAM variability

Authors:

Srivatsan Chellappa,

Nathan Hindman,

Jyothi Velamala,

Lawrence T. ClarkAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 711 - 716

https://doi.org/10.1145/1837274.1837454

Published: 13 June 2010 Publication History

Abstract

Measurement and extraction of as fabricated SRAM cell variability is essential to process improvement and robust design. This is challenging in practice, due to the complexity in the test procedure and requisite numerical analysis. This work proposes a new singleended test procedure for SRAM cell write margin measurement. Moreover, an efficient decomposition method is developed to extract transistor threshold voltage (V_TH) variations from the measurements, allowing accurate determination of SRAM cell stability. The entire approach is demonstrated in a 90nm test chip with 32K cells. The advantages of the proposed method include: (1) a single-ended SRAM test structure with no disturbance to SRAM operations; (2) a convenient test procedure that only requires quasistatic control of external voltages; and (3) a non-iterative method that extracts the V_TH variation of each transistor from eight measurements. The new procedure enables accurate predictions of SRAM performance variability. As validated with 90nm data of write margin and data retention voltage, the prediction error from extracted V_TH variations is < 4% at all corners.

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Cited By

Misawa NKurata HKumeno KNanjo RKai MEma TSole M(2017)SNM analytical approach to robust subthreshold SRAM operation based on the 55nm DDC technology2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)10.1109/S3S.2017.8308741(1-2)Online publication date: Oct-2017
https://doi.org/10.1109/S3S.2017.8308741
Chellappa SClark L(2016)SRAM-Based Unique Chip Identifier TechniquesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.244575124:4(1213-1222)Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2445751
Chellappa SDey AClark L(2011)Improved circuits for microchip identification using SRAM mismatch2011 IEEE Custom Integrated Circuits Conference (CICC)10.1109/CICC.2011.6055318(1-4)Online publication date: Sep-2011
https://doi.org/10.1109/CICC.2011.6055318

Index Terms

In-situ characterization and extraction of SRAM variability
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Hardware validation

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Published In

cover image ACM Conferences

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2010

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DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

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Cited By

Misawa NKurata HKumeno KNanjo RKai MEma TSole M(2017)SNM analytical approach to robust subthreshold SRAM operation based on the 55nm DDC technology2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)10.1109/S3S.2017.8308741(1-2)Online publication date: Oct-2017
https://doi.org/10.1109/S3S.2017.8308741
Chellappa SClark L(2016)SRAM-Based Unique Chip Identifier TechniquesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.244575124:4(1213-1222)Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2445751
Chellappa SDey AClark L(2011)Improved circuits for microchip identification using SRAM mismatch2011 IEEE Custom Integrated Circuits Conference (CICC)10.1109/CICC.2011.6055318(1-4)Online publication date: Sep-2011
https://doi.org/10.1109/CICC.2011.6055318

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