research-article

Hardware that produces bounded rather than exact results

Author:

Melvin BreuerAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 871 - 876

https://doi.org/10.1145/1837274.1837493

Published: 13 June 2010 Publication History

Abstract

Technological achievements have made it possible to: fabricate CMOS circuits with over a billion transistors; implement Boolean operations using quantum devices and/or the spin of an electron; implement transformations using bio and molecular based cells. Problems with many of these technologies are due to such factors as process variations, defects and impurities in materials and solutions, and noise. Consequently, many systems built from these technologies operate imperfectly. Luckily there are many complex and large-market systems (applications) that tolerate acceptable though not always correct results. In addition, there is emerging a body of mathematical analysis related to imperfect computation. In this paper we first introduce the concepts of acceptable error-tolerance and acceptable performance degradation, and demonstrate how important attributes of these concepts can be quantified. We interlace this discussion with several examples of systems that can effectively employ these two concepts. Next we mention several immerging technologies that motivate the need to study these concepts as well as related mathematical paradigms. Finally we will list a few CAD issues that are needed to support this new form of technological revolution.

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Cited By

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cover image ACM Conferences

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2010

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National Science Foundation

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DAC '10

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EDAC
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DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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https://doi.org/10.1109/ACCESS.2024.3463182
Sudheshna BVudadha CWali PKamath G(2023)An Approximate Full-Adder to Eliminate Carry Propagation in Lower Significant Stage of a Multi-Digit Adder2023 International Conference on Computer, Electronics & Electrical Engineering & their Applications (IC2E3)10.1109/IC2E357697.2023.10262637(1-6)Online publication date: 8-Jun-2023
https://doi.org/10.1109/IC2E357697.2023.10262637
Stanley-Marbell PRinard M(2017)Error-Efficient Computing SystemsFoundations and Trends in Electronic Design Automation10.1561/100000004911:4(362-461)Online publication date: 18-Dec-2017
https://dl.acm.org/doi/10.1561/1000000049
Park YKhajeh AShin JKurdahi FEltawil ADutt N(2017)Microarchitecture-Level SoC DesignHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_28-2(1-46)Online publication date: 11-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_28-2
Park YKhajeh AShin JKurdahi FEltawil ADutt N(2017)Microarchitecture-Level SoC DesignHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_28(867-913)Online publication date: 27-Sep-2017
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Beg A(2016)Modeling the Probabilities of Failures of 22 nm CMOS Logic Cells2016 Third International Conference on Mathematics and Computers in Sciences and in Industry (MCSI)10.1109/MCSI.2016.028(94-99)Online publication date: Aug-2016
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Soeken MGrobe DChandrasekharan ADrechsler R(2016)BDD minimization for approximate computing2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2016.7428057(474-479)Online publication date: Jan-2016
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Ichihara HInaoka TIwagaki TInoue T(2015)Logic simplification by minterm complement for error tolerant applicationProceedings of the 2015 33rd IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2015.7357089(94-100)Online publication date: 18-Oct-2015
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Ichihara HKamei JIwagaki TInoue T(2015)A practical approach for logic simplification based on fault acceptability for error tolerant application2015 20th IEEE European Test Symposium (ETS)10.1109/ETS.2015.7138727(1-2)Online publication date: May-2015
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Prasanth VParekhji RAmrutur B(2015)Improved Methods for Accurate Safety Analysis of Real-Life SystemsProceedings of the 2015 IEEE 24th Asian Test Symposium (ATS)10.1109/ATS.2015.37(175-180)Online publication date: 22-Nov-2015
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