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Fast identification of operating current for toggle MRAM by spiral search

Published:13 June 2010Publication History

ABSTRACT

Magnetic Random Access Memory (MRAM) is a non-volatile memory which is widely studied for its high speed, high density, small cell size, and almost unlimited endurance. However, for deep-submicron process technologies, significant variation in MRAM cells' operating regions results in write failures in cells and reduces the production yield. Currently, memory designers characterize failed MRAM chips to find a suitable current level for reconfiguring their operating current, which is time-consuming. In this paper, we propose an efficient operating current search method and a built-in circuit for toggle MRAM, which can rapidly find a customized operating current for each MRAM chip. With the built-in circuit, an MRAM chip can dynamically reconfigure its operating current automatically. Production yield and product life-time thus can be increased.

References

  1. M. Durlam, Y. Chung, M. DeHerrera, B. N Engel, G. Grynkewich, B. Martino, B. Nguyen, J. Salter, P. Shah, and J. M. Slaughter, "MRAM Memory for Embedded and Stand Alone Systems", in Proc. IEEE Int'l Conf. on IC Design & Technology (ICICDT), pp. 1--4, May 2007.Google ScholarGoogle ScholarCross RefCross Ref
  2. M. Durlam, B. Craigo, M. DeHerrera, B. N. Engel, G. Grynkewich, B. Huang, J. Janesky, M. Martin, B. Martino, J. Salter, J. M. Slaughter, L. Wise, and S. Tehrani, "Toggle MRAM: A highly-reliable Non-Volatile Memory", in Proc. IEEE Int'l Symp. on VLSI Technology, Systems and Applications (VLSI-TSA), pp. 1--2, April 2007.Google ScholarGoogle ScholarCross RefCross Ref
  3. N. Sakimura, R. Nebashi, H. Honjo, S. Saito, Y. Kato, and T. Sugibayashi, "A 500-MHz MRAM Macro for High-performance SoCs", in Proc. IEEE Asian Solid-State Cir. Conf. (ASSCC), pp. 3--5, Nov. 2008.Google ScholarGoogle ScholarCross RefCross Ref
  4. J. M. Slaughter, "Recent Advances in MRAM Technology", in Proc. IEEE Device Research Conference (DRC), pp. 245--245, June 2007.Google ScholarGoogle Scholar
  5. D. C. Worledge, P. L. Trouilloud, M. C. Gaidis, Y. Lu, D. W. Abraham, S. Assefa, S. Brown, E. Galligan, S. Kanakasabapathy, J. Nowak, E. O'Sullivan, R. Robertazzi, G. Wright, and W. J. Gallagher, "Materials and devices for reduced switching field toggle magnetic random access memory", Jour. of Appl. Phys., Vol. 100, pp. 074506-074506-6, Oct. 2006.Google ScholarGoogle ScholarCross RefCross Ref
  6. S. Tehrani, "Status and Outlook of MRAM Memory Technology (Invited)", in Proc. IEEE Int'l Electron Devices Meeting (IEDM), pp. 1--4, Dec. 2006.Google ScholarGoogle Scholar
  7. C.-L. Su, R.-F. Huang, C.-W. Wu, C.-C. Hung, M.-J. Kao, Y.-J. Chang, and W.-C. Wu, "MRAM defect analysis and fault modeling", in Proc. Int'l Test Conf. (ITC), Charlotte, pp. 124--133, Oct. 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. C.-L. Su, C.-W. Tsai, C.-W. Wu, C.-C. Hung, Y.-S. Chen, and M.-J. Kao, "Testing MRAM for write disturbance fault", in Proc. Int'l Test Conf. (ITC), Santa Clara, Oct. 2006.Google ScholarGoogle Scholar
  9. C.-L. Su, C.-W. Tsai, C.-W. Wu, C.-C. Hung, Y.-S. Chen, D.-Y. Wang, Y.-J. Lee, and M.-J. Kao, "Write disturbance modeling and testing for MRAM", IEEE Trans. on VLSI Systems, vol. 16, no. 3, pp. 277--288, Mar. 2008 Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. K. Shimura, N. Ohshima, S. Miura, R. Nebashi, T. Suzuki, H. Hada, S. Tahara, H. Aikawa, T. Ueda, T. Kajiyama, and H. Yoda, "Magnetic and Writing Properties of Clad Lines Used in a Toggle MRAM", IEEE Trans. on Magnetic, vol. 42, pp. 2736--2738, Oct. 2006.Google ScholarGoogle ScholarCross RefCross Ref
  11. C.-C. Hung, Y.-J. Lee, M.-J. Kao, Y.-H. Wang, R.-F. Huang, W.-C. Chen, Y.-S. Chen, K.-H. Shen, and M.-J. Tsai, "Wide operation margin of toggle mode switching for magnetic random access memory with preceding negative pulse writing scheme", Applied Physics Letters, vol. 88, pp. 112501-112501--3, Mar. 2006.Google ScholarGoogle ScholarCross RefCross Ref
  12. J. Akerman, P. Brown, M. DeHerrera, M. Durlam, E. Fuchs, D. Gajewski, M. Griswold, J. Janesky, J. Nahas and S. Tehrani, "Demonstrated reliability of 4-Mb MRAM", IEEE Trans. on Device and Materials Reliability, vol. 4, pp. 428--435, Sept. 2004.Google ScholarGoogle ScholarCross RefCross Ref
  13. D. C. Worledge, "Spin flop switching for magnetic random access memory", Applied Physics Letters, vol. 84, pp. 4559--4561, May 2004.Google ScholarGoogle ScholarCross RefCross Ref
  14. L.-T. Wang, C.-W. Wu, and X. Wen, Design for Testability: VLSI Test Principles and Architectures, San Francisco: Elsevier (Morgan Kaufmann), pp. 465--467, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. C. Cheng, C.-T. Huang, J.-R Huang, C.-W. Wu, C.-J. Wey, and M.-C. Tsai, "BRAINS: A BIST Compiler for Embedded Memories", in Proc. IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems (DFTVS), pp. 299--307, Oct. 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Agilent Technologies, Manual of the Agilent 93000 SOC series, System Reference, June 2004.Google ScholarGoogle Scholar
  17. T. Sugibayashi, N. Sakimura, T. Honda, K. Nagahara, K. Tsuji, H. Numata, S. Miura, K. Shimura, Y. Kato, S. Saito, Y. Fukumoto, H. Honjo, T. Suzuki, K. Suemitsu, T. Mukai, K. Mori, R. Nebashi, S. Fukami, N. Ohshima, H. Hada, N. Ishiwata, N. Kasai, and S. Tahara, "A 16-Mb Toggle MRAM With Burst Modes", IEEE Jour. of Solid-State Circuits (JSSC), vol. 42, pp. 2378--2385, Nov. 2007.Google ScholarGoogle ScholarCross RefCross Ref

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        cover image ACM Conferences
        DAC '10: Proceedings of the 47th Design Automation Conference
        June 2010
        1036 pages
        ISBN:9781450300025
        DOI:10.1145/1837274

        Copyright © 2010 ACM

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        Publication History

        • Published: 13 June 2010

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