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Variation aware performance analysis of gain cell embedded DRAMs

Published: 18 August 2010 Publication History

Abstract

Gain cell embedded DRAMs are twice as dense as 6T SRAMs, are logic compatible, have decoupled read and write paths providing good low voltage margin, and can drive long bitlines with gain. In this work, we present a variation study of gain cell eDRAM performance using an industrial 1.2V, 65nm low power CMOS process. Two methods are proposed to analyze eDRAM performance which can be used for designing variation tolerant eDRAM circuits, developing redundancy techniques, and guiding the device optimization procedure.

References

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Klim, P. J., Barth, J., Reohr, W. R., et al., "A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS," Solid-State Circuits, IEEE Journal of, vol. 44, no. 4, pp. 1216--1226, 2009.
[2]
Nakayama, M., Sakakibara, H., Kusunoki, M., et al., "A 16 MB cache DRAM LSI with internal 35.8 GB/s memory bandwidth for simultaneous read and write operation," Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International. pp. 398--399, 472--3.
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Romanovsky, S., Katoch, A., Achyuthan, A., et al., "A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS," Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International. pp. 270--612.
[4]
Somasekhar, D., Yibin, Y., Aseron, P., et al., "2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology," Solid-State Circuits, IEEE Journal of, vol. 44, no. 1, pp. 174--185, 2009.
[5]
Chun, K. C., Jain, P., Lee, J. H., et al., "A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias," VLSI Circuits, 2009 Symposium on. pp. 134--135.
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Luk, W. K., Jin, C., Dennard, R. H., et al., "A 3-Transistor DRAM Cell with Gated Diode for Enhanced Speed and Retention Time," VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on. pp. 184--185.

Cited By

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  • (2020)Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9180875(1-5)Online publication date: Oct-2020
  • (2017)Analysis of 2T 1D memory cell with various active capacitors2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC)10.1109/ICOMICON.2017.8279129(1-6)Online publication date: Aug-2017
  • (2017)Comparative analysis of 2T, 3T and 4T DRAM CMOS cells2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC)10.1109/ICOMICON.2017.8279116(1-6)Online publication date: Aug-2017
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  1. Variation aware performance analysis of gain cell embedded DRAMs

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    cover image ACM Conferences
    ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
    August 2010
    458 pages
    ISBN:9781450301466
    DOI:10.1145/1840845
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 18 August 2010

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    Author Tags

    1. bitline delay
    2. embedded DRAM
    3. gain cell
    4. monte carlo simulation
    5. process variation

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    Cited By

    View all
    • (2020)Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9180875(1-5)Online publication date: Oct-2020
    • (2017)Analysis of 2T 1D memory cell with various active capacitors2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC)10.1109/ICOMICON.2017.8279129(1-6)Online publication date: Aug-2017
    • (2017)Comparative analysis of 2T, 3T and 4T DRAM CMOS cells2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC)10.1109/ICOMICON.2017.8279116(1-6)Online publication date: Aug-2017
    • (2017)Retention Time Modeling: The Key to Low-Power GC-eDRAMsGain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip10.1007/978-3-319-60402-2_3(27-48)Online publication date: 7-Jul-2017
    • (2017)Gain-Cell eDRAMs (GC-eDRAMs): Review of Basics and Prior ArtGain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip10.1007/978-3-319-60402-2_2(13-26)Online publication date: 7-Jul-2017
    • (2016)Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2015.251270663:2(222-232)Online publication date: Feb-2016
    • (2014)Variability impact on on-chip memory data paths2014 5th European Workshop on CMOS Variability (VARI)10.1109/VARI.2014.6957086(1-5)Online publication date: Sep-2014
    • (2013)A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power ModeIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2013.225265260:8(2030-2038)Online publication date: Aug-2013
    • (2012)A novel variation-tolerant 4T-DRAM cell with enhanced soft-error toleranceProceedings of the 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)10.1109/ICCD.2012.6378681(472-477)Online publication date: 30-Sep-2012
    • (2012)Review and classification of gain cell eDRAM implementations2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel10.1109/EEEI.2012.6377022(1-5)Online publication date: Nov-2012
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