skip to main content
10.1145/1840845.1840862acmconferencesArticle/Chapter ViewAbstractPublication PagesislpedConference Proceedingsconference-collections
research-article

Diet SODA: a power-efficient processor for digital cameras

Published: 18 August 2010 Publication History

Abstract

Power has become the most critical design constraint for embedded handheld devices. This paper proposes a power-efficient SIMD architecture, referred to as Diet SODA, for DSP applications. The key design idea is to apply near-threshold operation on a single instruction and multiple data (SIMD) architecture to significantly lower the power consumption. The major features of Diet SODA are very wide SIMD width, scatter/gather data prefetcher, and dual mode operation. A case study was performed on digital still camera(DSC) applications; the results show that Diet SODA achieves ~130x better performance and ~340x better energy efficiency than a DSP solution.

References

[1]
J. C. Chen and S.-Y. Chien, "CRISP: Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders," IEEE Transactions on Circuits and Systems for Video Technology, vol. 18, no. 9, pp. 1223--1236, Sep. 2008.
[2]
K. Illgner, et al., "Programmable DSP platform for digital still cameras," Proceedings of IEEE International Conference on Acoustics, Speech, Signal Processing ICASSP âĂŹ99, vol. 4, pp. 2235--2238, Mar. 1999.
[3]
C. Chute, "Worldwide Digital Still Camera 2009âĂŞ¸S2013 Forecast," IDC, Apr. 2009.
[4]
H. Zen, et al., "A new digital signal processor for progressive scan CCD," IEEE Transactions on Consumer Electronics, vol. 4, no. 2, pp. 289--296, May 1998.
[5]
N. Nakano, et al., "Digital still camera system for megapixel CCD," IEEE Transactions on Consumer Electronics, vol. 44, no. 2, pp. 289--296, May 1998.
[6]
D. Talla, et al., "Anatomy of a portable digital mediaprocessor," IEEE Micro, vol. 24, no. 2, pp. 32--39, Mar.-Apr. 2004.
[7]
S. Agarwala, et al., "A 600MHz VLIW DSP," IEEE International Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002, vol. 2, pp. 38--390, 2002.
[8]
Nanoscale Integration and Modeling (NIMO) Group, "Predictive technology model (PTM)," {Online}. Available: http://www.eas.asu.edu/~ptm/. {Accessed Nov. 16, 2009}
[9]
B. Khailany, et al., "Imagine: media processing with streams," IEEE Micro, vol. 21, no. 2, pp. 35--46, Mar./Apr., 2001.
[10]
B. Khailany, et al., "A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing," IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 202--213, Jan. 2008.
[11]
Y. Lin, et al., "SODA: A low-power architecture for software radio," 33rd International Symposium on Computer Architecture, 2006. ISCA '06, pp. 89--101, 2006.
[12]
J. Glossner, et al., "The sandbridge SDR communications platform," Joint IST Workshop on Mobile Future, 2004 and the Symposium on Trends in Communications. SympoTIC '04, pp. ii-ix, 24--26, Oct. 2004.
[13]
K. V. Berkel, et al., "Vector Processing as an Enabler for Software-Define Radio in Handsets From 3G+WLAN Onwards," EURASIP Journal on Applied Signal Processing, pp. 2613--2625, Jan. 2005.
[14]
S. Knowles, "The SoC Future is Soft," IEEE Cambridge Processor Seminar, Dec. 2005.
[15]
O. Vermeulen, et al., "Ultra Fast Grey Scale Face Detection Using Vector SIMD Programming," Third International IEEE Conference on Signal-Image Technologies and Internet-Based System, 2007. SITIS '07, pp. 585--592, 16--18, Dec. 2007.
[16]
C. Wu, et al., "Mapping Vision Algorithms on SIMD Architecture Smart Cameras," First ACM/IEEE International Conference on Distributed Smart Cameras, 2007. ICDSC '07, pp. 27--34, 25--28, Sept. 2007.
[17]
T. Miyamori and K. Olukotun, "REMARC: ReconïňĄgurable multimedia array coprocessor," IEICE Trans. Inf. Syst., vol. E82-D, no. 2, pp. 389âĂŞ 397, 1999.
[18]
B. Mei, et al., "ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix," Lecture Notes in Computer Science, vol. 2778/2003, pp. 61âĂŞ70, Sep. 2003.
[19]
A. Cappelli, et al., "XiSystem: a XiRisc-based SoC with a reconfigurable IO module," IEEE International Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005, vol. 1 10--10, pp. 19661âĂŞ593, Feb. 2005.
[20]
B Zhai, et al., "Energy efficient near-threshold chip multi-processing," in Proc. of the ACM/IEEE International Symposium on Low-Power Electronics Design, pp. 32--37, 2007.
[21]
B. Bayer, "Color Imaging Arrary", U.S.Patent 3 971 065, Jul. 1976.
[22]
D. Philips, "Image Processing in C", R&D Publications Inc., 1994.
[23]
A. Wang and A. Chandrakasan, "A 180mV FFT processor using subthreshold circuit techniques," in Proc. of the IEEE International Solid-State Circuits Conference, pp. 292--529, 2004.

Cited By

View all
  • (2021)Customizable Vector Acceleration in Extreme-Edge Computing: A RISC-V Software/Hardware Architecture Study on VGG-16 ImplementationElectronics10.3390/electronics1004051810:4(518)Online publication date: 23-Feb-2021
  • (2021)Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing CoresIEEE Micro10.1109/MM.2021.305096241:2(64-71)Online publication date: Mar-2021
  • (2019)A templated programmable architecture for highly constrained embedded HD video processingJournal of Real-Time Image Processing10.1007/s11554-018-0808-616:1(143-160)Online publication date: 1-Feb-2019
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
August 2010
458 pages
ISBN:9781450301466
DOI:10.1145/1840845
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

In-Cooperation

  • IEEE CAS

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 August 2010

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. SIMD
  2. digital still cameras
  3. dynamic voltage scaling
  4. near-threshold

Qualifiers

  • Research-article

Conference

ISLPED'10
Sponsor:

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)3
  • Downloads (Last 6 weeks)0
Reflects downloads up to 22 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2021)Customizable Vector Acceleration in Extreme-Edge Computing: A RISC-V Software/Hardware Architecture Study on VGG-16 ImplementationElectronics10.3390/electronics1004051810:4(518)Online publication date: 23-Feb-2021
  • (2021)Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing CoresIEEE Micro10.1109/MM.2021.305096241:2(64-71)Online publication date: Mar-2021
  • (2019)A templated programmable architecture for highly constrained embedded HD video processingJournal of Real-Time Image Processing10.1007/s11554-018-0808-616:1(143-160)Online publication date: 1-Feb-2019
  • (2017)A 12-bit 4928 3264 pixel CMOS image signal processor for digital still camerasIntegration, the VLSI Journal10.1016/j.vlsi.2017.06.00559:C(206-217)Online publication date: 1-Sep-2017
  • (2017)Embedded Memories: IntroductionGain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip10.1007/978-3-319-60402-2_1(1-12)Online publication date: 7-Jul-2017
  • (2016)Enabling the heterogeneous accelerator model on ultra-low power microcontroller platformsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972090(1201-1206)Online publication date: 14-Mar-2016
  • (2016)Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/285603221:3(1-23)Online publication date: 11-May-2016
  • (2016)Accelerated Visual Context Classification on a Low-Power SmartwatchIEEE Transactions on Human-Machine Systems10.1109/THMS.2016.2623482(1-12)Online publication date: 2016
  • (2016)A low power software-defined-radio baseband processor for the Internet of Things2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446052(40-51)Online publication date: Mar-2016
  • (2016)PULPJournal of Signal Processing Systems10.1007/s11265-015-1070-984:3(339-354)Online publication date: 1-Sep-2016
  • Show More Cited By

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media