ABSTRACT
Resonant rotary clocking is a low power-high speed clock distribution technology for the modern VLSI circuits. Alternative topological implementations of rotary clocking with non-regular custom rings have been proposed in literature. In this paper, the impact of parasitics of the non-regular topological geometries on the rotary operating characteristics is presented. In particular, partial element equivalent circuit (PEEC) analysis is used to show that the corner geometry in a custom ring increases the mutual inductance approximately by 80%. Also, SPICE simulations are performed where the parasitics due to the topological factors are incorporated for an 8% increased accuracy in simulation. Further, the power dissipation on the rotary ring is analyzed with varying number of corners. When tested with the IBM R1-R5 benchmark circuits, the total power dissipated on a custom ring (corners between 4 and 12) is within ±5% of the total power dissipated on a regular ring(4 corners).
- E. Bogatin. Signal Integrity - Simplified. Prentice Hall, 2004. Google ScholarDigital Library
- V. H. Cordero and S. P. Khatri. Clock distribution scheme using coplanar transmission lines. In Proceedings of the Design, Automation and Test in Europe (DATE), pages 985--990, Mar. 2008. Google ScholarDigital Library
- T. C. Edwards and M. B. Steer. Foundations of Interconnect and Microstrip Design. May 2000.Google Scholar
- P. Gronowski, W. Bowhill, R. Preston, M. Gowan, and R. Allmon. High performance microprocessor design. IEEE Journal of Solid-State Circuits, 33(5):676--686, May 1998.Google ScholarCross Ref
- F. W. Grover. Inductance Calculations: Working Formulas and Tables. Instrument Society of America, 1962.Google Scholar
- V. Honkote and B. Taskin. Custom rotary clock router. In Proceedings of IEEE International Conference on Computer Design (ICCD), pages 114--119, Oct. 2008.Google ScholarCross Ref
- V. Honkote and B. Taskin. Zero clock skew synchronization with rotary clocking technology. In Proceedings of IEEE International Symposium on Quality of Electronic Design (ISQED), pages 588--593, Mar. 2009. Google ScholarDigital Library
- G. D. Mercey. A 18GHz rotary traveling wave VCO in CMOS with I/Q outputs. In Proceedings of the European Solid-State Circuits Conference (ESSCIRC), pages 489--492, Sept. 2003.Google Scholar
- A. E. Ruehli. Equivalent circuit models for three dimensional multiconductor systems. IEEE Transactions on Microwave Theory and Techniques, 22(3):216--221, Mar. 1974.Google ScholarCross Ref
- Synopsys. HSPICE Signal Integrity User Guide, 2009.Google Scholar
- G. Venkataraman, J. Hu, and F. Liu. Integrated placement and skew optimization for rotary clocking. IEEE Transactions on Very Large Scale Integration Systems, 15(2):149--158, Feb. 2007. Google ScholarDigital Library
- J. Wood, T. Edwards, and S. Lipa. Rotary traveling-wave oscillator arrays: A new clock technology. IEEE Journal of Solid-State Circuits, 36(11):1654--1665, Nov. 2001.Google ScholarCross Ref
- R. B. Wu, C. N. Kuo, and K. K. Chang. Inductance and resistance computations for three-dimensional multiconductor interconnection structures. IEEE Transactions on Microwave Theory and Techniques, 40(2):262--271, Feb. 1992.Google Scholar
- Z. Yu and X. Liu. Power analysis of rotary clock. In Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 150--155, May 2005. Google ScholarDigital Library
- C. Zhuo, H. Zhang, R. Samanta, J. Hu, and K. Chen. Modeling, optimization and control of rotary traveling-wave oscillator. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), pages 476--480, Nov. 2007. Google ScholarDigital Library
Index Terms
- PEEC based parasitic modeling for power analysis on custom rotary rings
Recommendations
3-D Parasitic Modeling for Rotary Interconnects
VLSID '12: Proceedings of the 2012 25th International Conference on VLSI DesignResonant rotary clocking is a high-frequency, low-power technology for high performance integrated circuits (IC). The implementation of the rotary clocking technology requires long interconnects with varying geometric shape segments on the chip, which ...
Modeling and Analysis of Leakage Currents in Double-Gate Technologies
This paper models and analyzes subthreshold and gate leakage currents in different double-gate (DG) devices, namely, a doped body symmetric device with polysilicon gates, an intrinsic body symmetric device with metal gates, and an intrinsic body ...
Inductance Modeling for On-Chip Interconnects
As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate ...
Comments