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Customizing pattern set for test power reduction via improved X-identification and reordering

Published: 18 August 2010 Publication History

Abstract

In this paper we present a method to identify don't care locations in a fully specified set of vectors, considering both fault propagation path and fault activation path. We exploit the identified X bits to convert the original vector to low power vector by dictionary based approach to minimize both dynamic and runtime leakage power. The dynamic power as well as the runtime leakage power depends on the activity in the circuit and hence depends on the sequence in which the test vectors are fed to it. We present an approach based on Particle Swarm Optimization (PSO) for vector reordering. Experiments on ISCAS89 benchmark circuits validate the effectiveness of our work. We achieve a maximum of 86.63% at an average of 60.89% reduction in dynamic power, a maximum of 6.87% at an average of 5.28% savings in terms of leakage power and a maximum of 66.55% at an average of 50.11% savings in terms of total power with respect to the original compacted test set generated by Tetramax ATPG tool.

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Cited By

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  • (2017)Reordering Tests for Efficient Fail Data Collection and Tester Time ReductionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.262832125:4(1497-1505)Online publication date: 1-Apr-2017
  • (2017)Temperature and data size trade-off in dictionary based test data compressionIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00257:C(20-33)Online publication date: 1-Mar-2017
  • (2017)Leakage Reduction by Test Pattern ReorderingProceedings of the International Conference on Nano-electronics, Circuits & Communication Systems10.1007/978-981-10-2999-8_5(55-68)Online publication date: 25-Mar-2017
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    cover image ACM Conferences
    ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
    August 2010
    458 pages
    ISBN:9781450301466
    DOI:10.1145/1840845
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 18 August 2010

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    Author Tags

    1. don't care bits
    2. dynamic power
    3. runtime leakage power
    4. vector reordering
    5. x-fill

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    View all
    • (2017)Reordering Tests for Efficient Fail Data Collection and Tester Time ReductionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.262832125:4(1497-1505)Online publication date: 1-Apr-2017
    • (2017)Temperature and data size trade-off in dictionary based test data compressionIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00257:C(20-33)Online publication date: 1-Mar-2017
    • (2017)Leakage Reduction by Test Pattern ReorderingProceedings of the International Conference on Nano-electronics, Circuits & Communication Systems10.1007/978-981-10-2999-8_5(55-68)Online publication date: 25-Mar-2017
    • (2013)Test power minimization of VLSI circuits: A survey2013 Fourth International Conference on Computing, Communications and Networking Technologies (ICCCNT)10.1109/ICCCNT.2013.6726569(1-6)Online publication date: Jul-2013

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