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Clock network design for ultra-low power applications

Published: 18 August 2010 Publication History

Abstract

Robust design is a critical concern in ultra-low voltage operation due to large sensitivity to process and environmental variations. In particular, clock networks need careful attention to ensure robust distribution of well-defined clock signals to avoid setup and hold time violations. In this paper, we investigate the design methodology of robust clock networks for ultra-low voltage applications. A case study shows that an optimally-chosen clock network improves skew variation by 36× and energy consumption by 49%, compared to a typical clock network. Additionally, the impact of supply voltage and technology scaling on the optimal clock network construction is investigated.

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Cited By

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  • (2020)A Platform of Resynthesizing a Clock Architecture Into Power-and-Area Effective Clock TreesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.294951439:10(2475-2488)Online publication date: Oct-2020
  • (2019)A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based $In \,\,Situ$ Error Detection and Correction TechniqueIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.291079227:8(1886-1896)Online publication date: Aug-2019
  • (2019)SLECTS: Slew-Driven Clock Tree SynthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.2888958(1-11)Online publication date: 2019
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    cover image ACM Conferences
    ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
    August 2010
    458 pages
    ISBN:9781450301466
    DOI:10.1145/1840845
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 18 August 2010

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    Author Tags

    1. clock network
    2. robust design
    3. ultra-low power

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    View all
    • (2020)A Platform of Resynthesizing a Clock Architecture Into Power-and-Area Effective Clock TreesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.294951439:10(2475-2488)Online publication date: Oct-2020
    • (2019)A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based $In \,\,Situ$ Error Detection and Correction TechniqueIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.291079227:8(1886-1896)Online publication date: Aug-2019
    • (2019)SLECTS: Slew-Driven Clock Tree SynthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.2888958(1-11)Online publication date: 2019
    • (2019)Ultra-Low Voltage MicrocontrollersEfficient Design of Variation-Resilient Ultra-Low Energy Digital Processors10.1007/978-3-030-12485-4_4(87-126)Online publication date: 28-Mar-2019
    • (2018)Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery2018 Ninth International Green and Sustainable Computing Conference (IGSC)10.1109/IGCC.2018.8752126(1-8)Online publication date: Oct-2018
    • (2018)Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applicationsAustralian Journal of Electrical and Electronics Engineering10.1080/1448837X.2018.152710115:3(98-117)Online publication date: 9-Oct-2018
    • (2017)In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and OptimizationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.262559825:3(1032-1043)Online publication date: Mar-2017
    • (2017)Near- and Sub- $V_{t}$ Pipelines Based on Wide-Pulsed-Latch Design TechniquesIEEE Journal of Solid-State Circuits10.1109/JSSC.2017.271792752:9(2475-2487)Online publication date: Sep-2017
    • (2017)A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUsIEEE Journal of Solid-State Circuits10.1109/JSSC.2017.269324152:7(1904-1914)Online publication date: Jul-2017
    • (2017) A Sub-cm 3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications IEEE Journal of Solid-State Circuits10.1109/JSSC.2016.263846552:4(961-971)Online publication date: Apr-2017
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