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View all- Lin TChen S(2020)A Platform of Resynthesizing a Clock Architecture Into Power-and-Area Effective Clock TreesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.294951439:10(2475-2488)Online publication date: Oct-2020
- Kim SCerqueira JSeok M(2019)A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based $In \,\,Situ$ Error Detection and Correction TechniqueIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.291079227:8(1886-1896)Online publication date: Aug-2019
- Liu WSitik CSalman ETaskin BSundareswaran SHuang B(2019)SLECTS: Slew-Driven Clock Tree SynthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.2888958(1-11)Online publication date: 2019
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