Cited By
View all- Kanj RJoshi RNassif S(2011)The impact of statistical leakage models on design yield estimationVLSI Design10.1155/2011/4719032011(1-12)Online publication date: 1-Jan-2011
In this paper we model (numerically and analytically) and analyze sub-threshold, gate-to-channel tunneling, and edge direct tunneling leakage in Double Gate (DG) devices. We compare the leakage of different DG structures, namely, doped body symmetric ...
Low-voltage scaling limitations of memory-rich CMOS LSIs are one of the major problems in the nanoscale era because they cause the evermore-serious power crisis with device scaling. The problems stem from two unscalable device parameters: The first is ...
Scaling devices while maintaining reasonable short channel immunity requires gate oxide thickness of less than 20Ao for CMOS devices beyond the 70nm technology node. Low oxide thickness gives rise to considerable direct tunneling current (gate leakage). ...
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