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Dynamic indexing: concurrent leakage and aging optimization for caches

Published: 18 August 2010 Publication History

Abstract

Previous works have shown that the traditional implementations of power management (i.e., using power gating or voltage scaling) can also mitigate the aging effect induced by Negative Bias Temperature Instability (NBTI), due to the partial recovery that occurs during the idle intervals used by power management. However, such a potential has been exploited only partially because of the different nature of energy and aging: as a performance figure, aging is affected by the worst idleness pattern. Therefore, large potential energy savings usually turn into limited aging reductions.
We address this problem in the context of caches, for which idleness is related to their access pattern. We propose a dynamic indexing scheme, in which the cache indexing function is changed over time in order to uniformly distribute the idleness over all the cache lines. In this way it is possible to fully use the leakage optimization potential and to extend the lifetime of a cache.
Experimental analysis shows that it is possible to obtain caches that are effectively aging-free, without any penalty in leakage energy reduction.

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  • (2021)A Comprehensive Assessment of Current Trends in Negative Bias Temperature Instability (NBTI) Deterioration2021 7th International Conference on Signal Processing and Communication (ICSC)10.1109/ICSC53193.2021.9673357(271-276)Online publication date: 25-Nov-2021
  • (2019)Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width ValuesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.290948827:7(1675-1684)Online publication date: Jul-2019
  • (2018) $In~Situ$ and In-Field Technique for Monitoring and Decelerating NBTI in 6T-SRAM Register FilesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.285652826:11(2241-2253)Online publication date: Nov-2018
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    cover image ACM Conferences
    ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
    August 2010
    458 pages
    ISBN:9781450301466
    DOI:10.1145/1840845
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 18 August 2010

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    Author Tags

    1. NBTI
    2. aging
    3. leakage optimization
    4. memory hierarchy

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    View all
    • (2021)A Comprehensive Assessment of Current Trends in Negative Bias Temperature Instability (NBTI) Deterioration2021 7th International Conference on Signal Processing and Communication (ICSC)10.1109/ICSC53193.2021.9673357(271-276)Online publication date: 25-Nov-2021
    • (2019)Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width ValuesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.290948827:7(1675-1684)Online publication date: Jul-2019
    • (2018) $In~Situ$ and In-Field Technique for Monitoring and Decelerating NBTI in 6T-SRAM Register FilesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.285652826:11(2241-2253)Online publication date: Nov-2018
    • (2014)Cache aging reduction with improved performance using dynamically re-sizable cacheProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616821(1-6)Online publication date: 24-Mar-2014
    • (2014)Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance DegradationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.227854922:8(1705-1715)Online publication date: Aug-2014
    • (2013)Combating NBTI-induced aging in data cachesProceedings of the 23rd ACM international conference on Great lakes symposium on VLSI10.1145/2483028.2483096(215-220)Online publication date: 2-May-2013
    • (2013)Energy-optimal SRAM supply voltage scheduling under lifetime and error constraintsProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488870(1-6)Online publication date: 29-May-2013
    • (2013)Assessment of Circuit Optimization Techniques Under NBTIIEEE Design & Test10.1109/MDAT.2013.226665130:6(40-49)Online publication date: Dec-2013
    • (2012)Application-specific memory partitioning for joint energy and lifetime optimizationProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492801(364-369)Online publication date: 12-Mar-2012
    • (2012)Energy-optimal caches with guaranteed lifetimeProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design10.1145/2333660.2333696(141-146)Online publication date: 30-Jul-2012
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