ABSTRACT
Near-Threshold Circuits achieve ultra-low energy operating with significant performance improvement and noise immunity as compared to sub-threshold circuits. However, near-threshold circuit performance is highly sensitive to static and dynamic threshold voltage variations. This makes designing circuits for a target performance very difficult, and post-silicon tunability is required to achieve performance targets without taking huge design margins. In this work, we tackle this problem by proposing a novel dual-Vdd technique for near-threshold operation and show that one can tune the performance of a circuit in a fine-grained manner by powering an optimal sub-set of rows with a slightly higher supply voltage than the rest, without incurring the large cost of distributed level shifters. By varying the percentage of rows at a slightly higher voltage, one can trade-off performance and power in a fine-grained manner. Experimental results show that by employing our dual-Vdd technique, we can improve the performance of several benchmarks up-to 45% while achieving more than 50% lower power as compared to single-Vdd implementations.
- Bo Zhai et.al, "Theoretical and Practical Limits of Dynamic Voltage Scaling," ACM/IEEE DAC, pp. 868--873, USA, 2004. Google ScholarDigital Library
- R. G. Dreslinski et.al, "Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits," Proceedings of the IEEE, vol. 98, no. 2, pp. 253--266, February 2010,Google ScholarCross Ref
- Markovic, D. et.al, "Ultralow-Power Design in Near-Threshold Region," Proceedings of the IEEE, vol. 98, no. 2, pp. 237--252, February 2010.Google ScholarCross Ref
- Bo Zhai, et.al, "Energy efficient near-threshold chip multi-processing," ACM ISLPED, pp. 32--37, USA, 2007. Google ScholarDigital Library
- R. Dreslinski, et.al, "An energy efficient parallel architecture using near threshold operation," IEEE PACT, pp. 175--185, Romania, 2007. Google ScholarDigital Library
- B. Calhoun, A. Wang and A. Chandrakasan, "Modeling and sizing for minimum energy operation in subthreshold circuits," IEEE Journal of Solid-State Circuits, vol. 40, no. 9, pp. 1778--1786, September 2005.Google ScholarCross Ref
- David Bol, et. al, "Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic," ACM ISLPED, pp. 3--8, USA, 2009. Google ScholarDigital Library
- David Bol, et.al, "Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits," ACM ISLPED, pp. 21--26, USA, 2009. Google ScholarDigital Library
- S. Hanson, et.al, "Exploring variability and performance in a sub-200-mV processor," IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 881--891, April 2008.Google ScholarCross Ref
- Mingoo Seok, et.al, "Optimal technology selection for minimizing energy and variability in low voltage applications," ACM ISLPED, pp. 9--14, USA, 2008. Google ScholarDigital Library
- N. Verma, J. Kwong, A. P. Chandrakasan, "Nanometer MOSFET variation in minimum energy subthreshold circuits," IEEE Transactions on Electron Devices, vol.55, no. 1, pp. 163--174, January 2008.Google ScholarCross Ref
- R. Gonzalez, B. M. Gordon, M. A. Horowitz, "Supply and threshold voltage scaling for low power CMOS," IEEE Journal of Solid-State Circuits, vol. 32, no. 8, pp. 1210--1216, August 1997.Google ScholarCross Ref
- H. Soeleman and k. Roy, "Ultra-low power digital subthreshold logic circuits," IEEE ISLPED, pp. 94--96, USA, 1999. Google ScholarDigital Library
- A. Wang, A. Chandrakasan, "A 180mV FFT processor using subthreshold circuit techniques," IEEE ISSCC, pp. 292--295, USA, 2004.Google Scholar
- B. Zhai, et.al, "A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency," IEEE VLSI-Symp, pp.154--155, USA, 2006.Google Scholar
- C. Kim, H. Soeleman, K. Roy, "Ultra-Low-Power DLMS Adaptive Filter for Hearing Aid Applications," IEEE Transactions on VLSI Systems, vol. 11, no. 6, pp. 1058--1067, December 2003. Google ScholarDigital Library
- Ali Keshavarzi, et.al, "Technology scaling behavior of optimum reverse body bias for Standby leakage power reduction in CMOS IC's," ACM ISLPED, pp. 252--254, USA, 1999. Google ScholarDigital Library
- Yu Pu, et.al, "An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply," IEEE ISSCC, pp. 146--147, USA, 2009.Google Scholar
- S. Sakiyama et.al, "An On-Chip High-Efficiency and Low-Noise DC/DC Converter Using Divided Switches with Current Control Technique," IEEE ISSCC, pp. 156--158, USA, 1999.Google Scholar
- Siyuan Zhou, and Gabriel, "A High Efficiency, Soft Switching DC-DC Converter With Adaptive Current-Ripple Control for Portable Applications," IEEE Transactions on Circuits and Systems, vol. 53, no. 4, pp. 319--323, April 2006.Google ScholarCross Ref
- T Hirose, T Asai, and Y Amemiya, "Power-supply circuits for ultralow-power subthreshold MOS-LSIs," IEICE Electronics Express, vol. 3, no. 22, pp. 464--468, November 2006.Google ScholarCross Ref
- B. Nezamfar et.al, "Energy-Performance Tunable Logic," IEEE CICC, pp. 183--186, USA, 2009.Google Scholar
- B. Zhai, S. Pant, et.al, "Energy efficient subthreshold processor design," IEEE Transactions on VLSI Systems, vol. 17, no. 8, pp. 1127--1137, August 2009. Google ScholarDigital Library
- Michael Keating, David Flynn, Robert Aitken, Alan Gibsons and Kaijian Shi, Low Power Methodology Manual for System on Chip Design, Springer Publications, NewYork, 2007. Google ScholarDigital Library
Index Terms
- Automatic synthesis of near-threshold circuits with fine-grained performance tunability
Recommendations
Yield-driven near-threshold SRAM design
Voltage scaling is desirable in static RAM (SRAM) to reduce energy consumption. However, commercial SRAM is susceptible to functional failures when VDD is scaled down. Although several published SRAM designs scale VDD to 200-300 mV, these designs do not ...
Low power shift register using MTCMOS edge-trigger D flip flop transmission gate in sub-threshold region
MINO'08: Proceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronicslow power design is most required nowadays due to scaling down the technology where minimizing the voltage level is the most effective way to minimize the power consumption. This paper presents the design and implementation of a low power Complementary ...
Design of sub-threshold current memory circuit for low power ADC
In this paper, it is proposed that the current memory circuit should be operated in sub-threshold region for low power of Analog to Digital Converter (ADC).When to store the sampling information of the analog signal and to pass to the next stage is used ...
Comments