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Finding an upper bound on the increase in execution time due to contention on the memory bus in COTS-based multicore systems

Published: 01 January 2010 Publication History

Abstract

Contention on the memory bus in COTS based multicore systems is becoming a major determining factor of the execution time of a task. Analyzing this extra execution time is non-trivial because (i) bus arbitration protocols in such systems are often undocumented and (ii) the times when the memory bus is requested to be used are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. We present a method for finding an upper bound on the extra execution time of a task due to contention on the memory bus in COTS based multicore systems. This method makes no assumptions on the bus arbitration protocol (other than assuming that it is work-conserving).

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  • (2019)Survey of Memory, Timing, and Power Management Verification Methods for Multi-core Processors2019 IEEE 10th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON)10.1109/IEMCON.2019.8936198(0110-0119)Online publication date: Oct-2019
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Published In

cover image ACM SIGBED Review
ACM SIGBED Review  Volume 7, Issue 1
Special Issue on the Work-in-Progress (WIP) Session at the 2009 IEEE Real-Time Systems Symposium (RTSS)
January 2010
27 pages
EISSN:1551-3688
DOI:10.1145/1851166
Issue’s Table of Contents

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 January 2010
Published in SIGBED Volume 7, Issue 1

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Cited By

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  • (2019)Survey of Memory, Timing, and Power Management Verification Methods for Multi-core Processors2019 IEEE 10th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON)10.1109/IEMCON.2019.8936198(0110-0119)Online publication date: Oct-2019
  • (2018)Schedulability Analysis of Tasks with Corunner-Dependent Execution TimesACM Transactions on Embedded Computing Systems10.1145/320340717:3(1-29)Online publication date: 22-May-2018
  • (2017)Schedulability and Memory Interference Analysis of Multicore Preemptive Real-time SystemsProceedings of the 8th ACM/SPEC on International Conference on Performance Engineering10.1145/3030207.3030233(263-274)Online publication date: 17-Apr-2017
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  • (2016)Bounding and reducing memory interference in COTS-based multi-core systemsReal-Time Systems10.1007/s11241-016-9248-152:3(356-395)Online publication date: 1-May-2016
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