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A software-SVM-based transactional memory for multicore accelerator architectures with local memory

Published: 11 September 2010 Publication History

Abstract

We propose a software transactional memory (STM) for heterogeneous multicores with small local memory. The heterogeneous multicore architecture consists of a general-purpose processor element (GPE) and multiple accelerator processor elements (APEs). The GPE is typically backed by a deep, on-chip cache hierarchy and hardware cache coherence. On the other hand, the APEs have small, explicitly addressed local memory that is not coherent with the main memory. Programmers of such multicore architectures suffer from explicit memory management and coherence problems. The STM for such multicores can alleviate the burden of the programmer and transparently handle data transfers at run time. Moreover, it makes the programmer free from controlling locks. Our TM is based on an existing software SVM for the accelerator architecture. The software SVM exploits software-managed caches and coherence protocols between the GPE and APEs. We also propose an optimization technique, called abort prediction, for the TM. It blocks a transaction from running until the chance of potential conflicts is eliminated. We implement the TM system and the optimization technique for a single Cell BE processor and evaluate their effectiveness with six compute-intensive benchmark applications.

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Cited By

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  • (2012)A transactional runtime system for the Cell/BE architectureJournal of Parallel and Distributed Computing10.1016/j.jpdc.2012.08.00172:12(1535-1546)Online publication date: 1-Dec-2012

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Published In

cover image ACM Conferences
PACT '10: Proceedings of the 19th international conference on Parallel architectures and compilation techniques
September 2010
596 pages
ISBN:9781450301787
DOI:10.1145/1854273

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 September 2010

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Author Tags

  1. heterogeneous multicores
  2. software shared virtual memory
  3. transactional memory

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PACT '10
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  • IFIP WG 10.3
  • IEEE CS TCPP
  • SIGARCH
  • IEEE CS TCAA

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Overall Acceptance Rate 121 of 471 submissions, 26%

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  • (2012)A transactional runtime system for the Cell/BE architectureJournal of Parallel and Distributed Computing10.1016/j.jpdc.2012.08.00172:12(1535-1546)Online publication date: 1-Dec-2012

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