David Bol
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Abstract
Subthreshold operation of digital circuits enables minimum energy consumption. In this article, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45nm CMOS node. We demonstrate by circuit simulation and analytical modeling that this increase comes from the combined effects of variability, gate leakage, and Drain-Induced Barrier Lowering (DIBL) effect. We then investigate the new impact of individual MOSFET parameters Lg, Vt, and Tox on Emin in sub-45nm technologies. We further propose an optimum MOSFET selection, which favors low-Vt mid-Lg devices in 45nm CMOS technology. The use of such optimum MOSFETs yields 35% Emin reduction for a benchmark multiplier with good speed performances and negligible area overhead. This optimum MOSFET selection can easily be integrated into a standard EDA tool flow by appropriate selection of the standard cell library.
We finally demonstrate that undoped-channel fully-depleted Silicon-On-Insulator (SOI) technology brings 60% Emin reduction with baseline MOSFETs thanks to strong mitigation of variability and short-channel effects. This study reveals a new (à priori counterintuitive) paradigm in device optimization for subthreshold logic: relaxing gate leakage constraints to improve robustness against short-channel effects and variability. Additionally, we propose pre-Silicon BSIM4 MOSFET model cards for realistic subthreshold circuit simulations including variability in bulk and fully depleted SOI technologies, which are made available online.
- Asenov, A., Brown, A., Davies, J., Kaya, S., and Slavcheva, G. 2003. Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale mosfets. IEEE Trans. Electron. Devices 50, 9, 1837--1852.Google Scholar
Cross Ref
- Bol, D., Ambroise, R., Flandre, D., and Legat, J.-D. 2008. Sub-45nm fully-depleted soi cmos subthreshold logic for ultra-low-power applications. In Proceedings of the International SOI Conference. IEEE, 57--58.Google Scholar
- Bol, D., Ambroise, R., Flandre, D., and Legat, J.-D. 2009a. Interests and limitations of technology scaling for subthreshold logic. IEEE Trans. VLSI Syst. 17, 10, 1508--1519. Google ScholarDigital Library
- Bol, D., Flandre, D., and Legat, J.-D. 2009b. Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits. In Proceedings of the International Symposium on Low-Power Electronics and Design. ACM, 21--26. Google ScholarDigital Library
- Bol, D., Kamel, D., Flandre, D., and Legat, J.-D. 2009c. Nanometer mosfet effects on the minimum-energy point of 45nm subthreshold logic. In Proceedings of the International Symposium on Low-Power Electronics and Design. ACM, 3--8. Google ScholarDigital Library
- Bol, D., Hocquet, C., Flandre, D., and Legat, J.-D. 2010. Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits. In Proceedings of the International Circuits and Systems Conference. IEEE, 1484--1487.Google Scholar
- Brown, A. R., Roy, G., and Asenov, A. 2007. Poly-si-gate-related variability in decananometer mosfets with conventional architecture. IEEE Trans. Electron. Devices 54, 11, 3056--3063.Google ScholarCross Ref
- Calhoun, B. and Chandrakasan, A. 2006. Ultra-dynamic voltage scaling (udvs) using subthreshold operation and local voltage dithering. IEEE J. Solid-State Circ. 41, 1, 238--245.Google ScholarCross Ref
- Calhoun, B., Wang, A., and Chandrakasan, A. 2005. Modeling and sizing for minimum energy operation in subthreshold circuits. IEEE J. Solid-State Circ. 40, 9, 1778--1786.Google ScholarCross Ref
- Cao, Y. and Clark, L. 2005. Mapping statistical process variations toward circuit performance variability: An analytical modeling approach. In Proceedings of the Design Automation Conference. ACM, 658--663. Google ScholarDigital Library
- Chandrakasan, A., Daly, D., Finchelstein, D., Kwong, J., Ramadass, Y., Sinangil, M., Sze, V., and Verma, N. 2010. Technologies for ultradynamic voltage scaling. Proc. IEEE 98, 2, 191--241.Google ScholarCross Ref
- Cheng, B., Roy, S., Brown, A., Millar, C., and Asenov, A. 2008. Statistical variations in 32nm thin-body sol devices and sram cells. In International Conference on Solid-State and Integrated-Circuit Technology. IEEE.Google Scholar
- Colinge, J. P. 2004. The soi mosfet. In Silicon-on-Insulator Technology: Materials to VLSI, 3rd. Springer, 151--246.Google Scholar
- Fenouillet-Beranger, C. 2007. Fully-Depleted soi technology using high-k and single-metal gate for 32nm node lstp applications featuring 0.179μm
2 6t-sram bitcell. In Proceedings of the International Electronics Device Meeting. IEEE, 267--270.Google Scholar
- Hanson, S., Zhai, B., Blauw, D., and Sylvester, D. 2006. Energy optimality and variability in subthreshold design. In Proceedings of the International Symposium on Low-Power Electronics and Design. ACM, 363--365. Google ScholarDigital Library
- Hanson, S., Seok, M., Sylvester, D., and Blauw, D. 2008. Nanometer device scaling in subthreshold logic and sram. IEEE Trans. Electron. Devices 55, 1, 175--185.Google ScholarCross Ref
- Kaul, H., Anders, M., Mathew, S., Hsu, S., Agarwal, A., Krishnamurthy, R., and Borkar, S. 2010. A 300mv 494gops/w reconfigurable dual-supply 4-way simd vector processing accelerator in 45nm cmos. IEEE J. Solid-State Circ. 45, 1, 95--102.Google ScholarCross Ref
- Kim, J.-J. and Roy, K. 2004. Double-gate mosfet subthreshold circuit for ultralow power applications. IEEE Trans. Electron. Devices 51, 9, 1468--1474.Google ScholarCross Ref
- Kwong, J., Ramadass, Y., Verma, N., and Chandrakasan, A. 2009. A 65nm sub-vt micro- controller with integrated sram and switched capacitor dc-dc converter. IEEE J. Solid-State Circ. 44, 1, 115--126.Google ScholarCross Ref
- Mizuno, T., Okamura, J., and Toriumi, A. 1993. Experimental study of threshold voltage fluctuations using an 8k mosfets array. In Proceedings of the Symposium on VLSI Technology. IEEE, 41--42.Google Scholar
- Mohapatra, N., Desai, M., Narendra, S., and Ramgopal, V. R. 2003. Modeling of parasitic capacitances in deep submicrometer conventional and high-dielectric mos transistors. IEEE Trans. Electron. Devices 50, 4, 959--966.Google ScholarCross Ref
- Numata, T. and Takagi, S. 2004. Device design for subthreshold slope and threshold voltage control in sub-100-nm fully-depleted soi mosfets. IEEE Trans. Electron. Devices 51, 12, 2161--2167.Google ScholarCross Ref
- Paul, B. and Roy, K. 2008. Oxide thickness optimization for digital subthreshold operation. IEEE Trans. Electron. Devices 55, 2, 685--688.Google ScholarCross Ref
- Paul, B., Raychowdhury, A., and Roy, K. 2005. Device optimization for digital subthreshold logic operation. IEEE Trans. Electron. Devices 52, 2, 237--247.Google ScholarCross Ref
- Paul, B. C., Bansal, A., and Roy, K. 2006. Underlap dgmos for digital subthreshold operation. IEEE Trans. Electron. Devices 53, 4, 910--913.Google ScholarCross Ref
- Pelgrom, M., Duinmaijer, A., and Welbers, A. 1989. Matching properties of mos transistors. IEEE J. Solid-State Circ. 24, 5, 1433--1440.Google ScholarCross Ref
- Pu, Y., de Gyvez, J., Corporaal, H., and Ha, Y. 2009. An ultra-low-energy/frame multi-standard jpeg co-processor in 65nm cmos with sub/near-threshold power supply. In Proceedings of the International Solid-State Circuit Conference. IEEE, 146--147.Google Scholar
- Raychowdhury, A., Fong, X., Chen, Q., and Roy, K. 2006. Analysis of super cut-off transistors for ultra-low power digital circuits. In Proceedings of the International Symposium on Low-Power Electronics and Design. ACM, 2--7. Google ScholarDigital Library
- Roy, G., Brown, A. R., Adamu-Lema, F., Roy, S., and Asenov, A. 2006. Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nanomosfets. IEEE Trans. Electron. Devices 53, 12, 3063--3070.Google ScholarCross Ref
- Seok, M., Hanson, S., Sylvester, D., and Blauw, D. 2007. Analysis and optimization of sleep modes in subthreshold circuit design. In Proceedings of the Design Automation Conference. ACM, 604--699. Google ScholarDigital Library
- Skotnicki, T., Fenouillet-Beranger, C., Gallon, C., Boeuf, F., Monfray, S., Payet, F., Pouydebasque, A., Szczap, M., Farcy, A., Arnaud, F., Clerc, S., Sellier, M., Cathignol, A., Schoellkopf, J.-P., Perea, E., Ferrant, R., and Mingam, H. 2008. Innovative materials, devices and cmos technologies for low-power mobile multimedia. IEEE Trans. Electron. Devices 55, 1, 96--130.Google ScholarCross Ref
- Soeleman, H. and Roy, K. 1999. Ultra-Low power digital subthreshold logic circuits. In Proceedings of the International Symposium on Low-Power Electronics and Design. ACM, 94--96. Google ScholarDigital Library
- Sze, V. and Chandrakasan, A. 2006. A 0.4-v uwb baseband processor. In Proceedings of the International Symposium on Low-Power Electronics and Design. ACM, 262--267. Google ScholarDigital Library
- Takahashi, O., Adams, C., Behnen, E., Chiang, O., Cottier, S., Coulman, P., Culp, J., Gervais, G., Gray, M., Itaka, Y., Johnson, C., Kono, F., L.Maurice, McCullen, K., Nguyen, L., Nishino, Y., Noro, H., Pille, J., Riley, M., Tokito, S., T.Wagner, and Yoshihara, H. 2008. Migration of cell broadband engine from 65nm soi to 45nm soi. In Proceedings of the International Solid-State Circuit Conference. IEEE, 86--87.Google Scholar
- Tsutsui, G., Saitoh, M., Nagumo, T., and Hiramoto, T. 2005. Impact of soi thickness fluctu- ation on threshold voltage variation in ultra-thin body soi mosfets. IEEE Trans. Nanotechnol. 40, 3, 369--373. Google ScholarDigital Library
- Verma, N., Kwong, J., and Chandrakasan, A. 2008. Nanometer mosfet variation in minimum energy subthreshold circuits. IEEE Trans. Electron. Devices 55, 1, 163--174.Google ScholarCross Ref
- Vitale, S., Wyatt, P., Checka, N., Kedzierski, J., and Keast, C. 2010. Fdsoi process tech- nology for subthreshold-operation ultralow-power electronics. Proc. IEEE 98, 2, 333--342.Google ScholarCross Ref
- Weber, O. 2008. High immunity to threshold voltage variability in undoped ultra-thin fdsoi mosfets and its physical understanding. In Proceedings of the International Electron Device Meeting. IEEE.Google ScholarCross Ref
- Zhai, B., Blauw, D., Sylvester, D., and Flautner, K. 2005. The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. IEEE Trans. VLSI Syst. 13, 11, 1239--1252. Google ScholarDigital Library
- Zhai, B., Dreslinski, R., Blaauw, D., Mudge, T., and Sylvester, D. 2007. Energy efficient near-threshold chip multi-processing. In Proceedings of the International Symposium on Low-Power Electronics and Design. ACM, 32--37. Google ScholarDigital Library
- Zhao, W. and Cao, Y. 2006. New generation of predictive technology model for sub-45nm early design exploration. IEEE Trans. Electron. Devices 53, 11, 2816--2823.Google ScholarCross Ref
Index Terms
- Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic---Mitigation at Technology and Circuit Levels
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