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Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications

Published: 24 October 2010 Publication History

Abstract

A streaming application, characterized by a kernel that can be broken down into independent tasks which can be executed in a pipelined fashion, inherently allows its implementation on a pipeline of Application Specific Instruction set Processors (ASIPs), called a pipelined MPSoC. The latency and throughput requirements of streaming applications put constraints on the design of such a pipelined MPSoC, where each ASIP has a number of available configurations differing by additional instructions, and instruction and data cache sizes. Thus, the design space of a pipelined MPSoC is all the possible combinations of ASIP configurations (design points).
In this paper, a methodology is proposed to optimize the area of a pipelined MPSoC under a latency or a throughput constraint. The final design point is a set of ASIP configurations with one configuration for each ASIP. We proposed an Integer Linear Programming (ILP) based solution to the area optimization problem under a latency constraint, and an algorithm for optimization of pipelined MPSoC area under a throughput constraint. The proposed solutions were evaluated using four streaming applications: JPEG encoder; JPEG decoder; MP3 encoder; and H.264 decoder. The time to find the Pareto front of each pipelined MPSoC was less than 4 minutes where design spaces had up to 1016 design points, illustrating the applicability of our approach.

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cover image ACM Conferences
CODES/ISSS '10: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
October 2010
348 pages
ISBN:9781605589053
DOI:10.1145/1878961
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 24 October 2010

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Author Tags

  1. design space exploration
  2. integer linear programming

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  • Research-article

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ESWeek '10
ESWeek '10: Sixth Embedded Systems Week
October 24 - 29, 2010
Arizona, Scottsdale, USA

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Overall Acceptance Rate 280 of 864 submissions, 32%

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  • (2021)Energy-Efficient System Design of Asymmetric Multiprocessor for Real-Time Streaming Applications2021 International Conference on Intelligent Technology and Embedded Systems (ICITES)10.1109/ICITES53477.2021.9637078(44-51)Online publication date: 31-Oct-2021
  • (2018)On the Design of Reliable Heterogeneous Systems via Checkpoint Placement and Core AssignmentProceedings of the 2018 Great Lakes Symposium on VLSI10.1145/3194554.3194642(475-478)Online publication date: 30-May-2018
  • (2018)Heterogeneous FPGA-Based Cost-Optimal Design for Timing-Constrained CNNsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285709837:11(2542-2554)Online publication date: Nov-2018
  • (2017)Optimal functional unit assignment and voltage selection for pipelined MPSoC with guaranteed probability on time performanceACM SIGPLAN Notices10.1145/3140582.308103652:5(41-50)Online publication date: 21-Jun-2017
  • (2017)Optimal functional unit assignment and voltage selection for pipelined MPSoC with guaranteed probability on time performanceProceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3078633.3081036(41-50)Online publication date: 21-Jun-2017
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  • (2016)Optimal functional-unit assignment and buffer placement for probabilistic pipelinesProceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.1145/2968456.2968467(1-10)Online publication date: 1-Oct-2016
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