research-article

Simplifying data path processing in next-generation routers

Authors:

Tilman WolfAuthors Info & Claims

ANCS '09: Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems

Pages 11 - 19

https://doi.org/10.1145/1882486.1882492

Published: 19 October 2009 Publication History

Abstract

Customizable packet processing is an important aspect of next-generation networks. Packet processing architectures using multi-core systems on a chip can be difficult to program. In our work, we propose a new packet processor design that simplifies packet processing by managing packet contexts in hardware. We show how such a design scales to large systems. Our results also show that the management of such a system is feasible with the proposed mapping algorithm.

References

[1]

Anderson, T., Peterson, L., Shenker, S., and Turner, J. Overcoming the Internet impasse through virtualization. Computer 38, 4 (Apr. 2005), 34--41.

Digital Library

[2]

Cisco Systems, Inc. The Cisco QuantumFlow Processor: CiscoŠs Next Generation Network Processor. San Jose, CA, Feb. 2008.

[3]

Decasper, D., Dittia, Z., Parulkar, G., and Plattner, B. Router Plugins - a modular and extensible software framework for modern high performance integrated services routers. In Proc. of ACM SIGCOMM 98 (Vancouver, BC, Sept. 1998), pp. 229--240.

Digital Library

[4]

Eatherton, W. The push of network processing to the top of the pyramid. In Keynote Presentation at ACM/IEEE Symposium on Architectures for Networking and Communication Systems (ANCS) (Princeton, NJ, Oct. 2005).

[5]

Feldmann, A. Internet clean-slate design: what and why? SIGCOMM Computer Communication Review 37, 3 (July 2007), 59--64.

Digital Library

[6]

Ganapathy, S., and Wolf, T. Design of a network service architecture. In Proc. of Sixteenth IEEE International Conference on Computer Communications and Networks (ICCCN) (Honolulu, HI, Aug. 2007), pp. 754--759.

[7]

Goglin, S. D., Hooper, D., Kumar, A., and Yavatkar, R. Advanced software framework, tools, and languages for the IXP family. Intel Technology Journal 7, 4 (Nov. 2003), 64--76.

[8]

Grunewald, M., Le, D. K., Kastens, U., Niemann, J.-C., Porrmann, M., Ruckert, U., Slowik, A., and Thies, M. Network application driven instruction set extensions for embedded processing clusters. In Proc. of the International Conference on Parallel Computing in Electrical Engineering (PARELEC) (Dresden, Germany, Sept. 2004), pp. 209--214.

Digital Library

[9]

Hutchinson, N. C., and Peterson, L. L. The x-kernel: An architecture for implementing network protocols. IEEE Transactions on Software Engineering 17, 1 (Jan. 1991), 64--76.

Digital Library

[10]

Intel Corporation. Intel Second Generation Network Processor, 2005. http://www.intel.com/design/network/products/npfamily/.

[11]

Kohler, E., Morris, R., Chen, B., Jannotti, J., and Kaashoek, M. F. The Click modular router. ACM Transactions on Computer Systems 18, 3 (Aug. 2000), 263--297.

Digital Library

[12]

Kokku, R., Riché, T., Kunze, A., Mudigonda, J., Jason, J., and Vin, H. A case for run-time adaptation in packet processing systems. In Proc. of the 2nd Workshop on Hot Topics in Networks (HOTNETS-II) (Cambridge, MA, Nov. 2003).

[13]

Kuhns, F., DeHart, J., Kantawala, A., Keller, R., Lockwood, J., Pappu, P., Richard, D., Taylor, D. E., Parwatikar, J., Spitznagel, E., Turner, J., and Wong, K. Design of a high performance dynamically extensible router. In Proc. of DARPA Active Networks Conference and Exhibition (San Francisco, CA, May 2002).

Digital Library

[14]

Lockwood, J. W., McKeown, N., Watson, G., Gibb, G., Hartke, P., Naous, J., Raghuraman, R., and Luo, J. NetFPGA--an open platform for gigabit-rate network switching and routing. In MSE '07: Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education (San Diego, CA, June 2007), pp. 160--161.

Digital Library

[15]

Milliken, W. C., and Dietz, J. Execution unit for a network processor. United States Patent 7,289,524, Oct. 2007.

[16]

Ramaswamy, R., and Wolf, T. PacketBench: A tool for workload characterization of network processing. In Proc. of IEEE 6th Annual Workshop on Workload Characterization (WWC-6) (Austin, TX, Oct. 2003), pp. 42--50.

[17]

Shah, N., Plishker, W., Ravindran, K., and Keutzer, K. NP-Click: A productive software development approach for network processors. IEEE Micro 24, 5 (Sept. 2004), 45--54.

Digital Library

[18]

Spalink, T., Karlin, S., Peterson, L., and Gottlieb, Y. Building a robust software-based router using network processors. In Proc. of the 18th ACM Symposium on Operating Systems Principles (SOSP) (Banff, AB, Oct. 2001), pp. 216--229.

Digital Library

[19]

Taylor, D. E., Turner, J. S., Lockwood, J. W., and Horta, E. L. Dynamic hardware plugins: Exploiting reconfigurable hardware for high-performance programmable routers. Computer Networks 38, 3 (Feb. 2002), 295--310.

Digital Library

[20]

Tennenhouse, D. L., and Wetherall, D. J. Towards an active network architecture. ACM SIGCOMM Computer Communication Review 26, 2 (Apr. 1996), 5--18.

Digital Library

[21]

Wolf, T. Challenges and applications for network-processor-based programmable routers. In Proc. of IEEE Sarnoff Symposium (Princeton, NJ, Mar. 2006).

[22]

Wolf, T., Weng, N., and Tai, C.-H. Run-time support for multi-core packet processing systems. IEEE Network 21, 4 (July 2007), 29--37.

Digital Library

[23]

Wu, Q., and Wolf, T. On runtime management in multi-core packet processing systems. In Proc. of ACM/IEEE Symposium on Architectures for Networking and Communication Systems (ANCS) (San Jose, CA, Nov. 2008).

Digital Library

[24]

Wu, Q., and Wolf, T. Design of a network service processing platform for data path customization. In Proc. of The Second ACM SIGCOMM Workshop on Programmable Routers for Extensible Services of TOmorrow (PRESTO) (Barcelona, Spain, Aug. 2009).

Digital Library

Cited By

Attig MBrebner G(2011)400 Gb/s Programmable Packet Parsing on a Single FPGAProceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems10.1109/ANCS.2011.12(12-23)Online publication date: 3-Oct-2011
https://dl.acm.org/doi/10.1109/ANCS.2011.12
Wu QShanbhag SWolf TLin BMogul JIyer R(2010)Fair multithreading on packet processors for scalable network virtualizationProceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems10.1145/1872007.1872009(1-11)Online publication date: 25-Oct-2010
https://dl.acm.org/doi/10.1145/1872007.1872009
Wu QChasaki DWolf T(2010)Implementation of a simplified network processor2010 International Conference on High Performance Switching and Routing10.1109/HPSR.2010.5580273(7-13)Online publication date: Jun-2010
https://doi.org/10.1109/HPSR.2010.5580273

Index Terms

Simplifying data path processing in next-generation routers
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
2. Networks
  1. Network components
    1. Intermediate nodes
      1. Routers

Recommendations

A Novel CAM/RAM Based Buffer Manager for Next Generation IP Routers
DELTA '02: Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)

This paper proposes an integrated CAM/RAM based buffer manager for next-generation IP routers. Buffer allocation is accomplished by inspecting the length field in the IP header of an incoming packet, the wasted buffer area is optimized, and the hardware ...
Next generation Tbit/sec routers and switches: traffic modeling, scheduling algorithms, and simulations

Scheduling algorithms for next generation multi Tbit/sec routers and switches are evaluated. Concurrently, available packet interconnections do not exceed a few hundreds Gbit/sec of aggregate throughput, making traffic modeling and computer simulations ...
Experimenting with buffer sizes in routers
ANCS '07: Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems

Recent theoretical results in buffer sizing research suggest that core Internet routers can achieve high link utilization, if they are capable of storing only a handful of packets. The underlying assumption is that the traffic is non-bursty, and that ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ANCS '09: Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems

October 2009

227 pages

ISBN:9781605586304

DOI:10.1145/1882486

General Chairs:
Peter Onufryk
IDT
,
K. K. Ramakrishnan
AT&T Labs - Research
,
Program Chairs:
Patrick Crowley
Washington University in St. Louis
,
John Wroclawski
USC

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGCOMM: ACM Special Interest Group on Data Communication
SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS\TCCA: TC on Computer Arhitecture

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 October 2009

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article

Funding Sources

Division of Computer and Network Systems

Conference

ANCS '09

Sponsor:

SIGCOMM
SIGARCH
IEEE-CS\TCCA

ANCS '09: Symposium on Architecture for Networking and Communications Systems

October 19 - 20, 2009

New Jersey, Princeton

Acceptance Rates

Overall Acceptance Rate 88 of 314 submissions, 28%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
142
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)1

Reflects downloads up to 27 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Attig MBrebner G(2011)400 Gb/s Programmable Packet Parsing on a Single FPGAProceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems10.1109/ANCS.2011.12(12-23)Online publication date: 3-Oct-2011
https://dl.acm.org/doi/10.1109/ANCS.2011.12
Wu QShanbhag SWolf TLin BMogul JIyer R(2010)Fair multithreading on packet processors for scalable network virtualizationProceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems10.1145/1872007.1872009(1-11)Online publication date: 25-Oct-2010
https://dl.acm.org/doi/10.1145/1872007.1872009
Wu QChasaki DWolf T(2010)Implementation of a simplified network processor2010 International Conference on High Performance Switching and Routing10.1109/HPSR.2010.5580273(7-13)Online publication date: Jun-2010
https://doi.org/10.1109/HPSR.2010.5580273

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten