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Design and performance analysis of a DRAM-based statistics counter array architecture

Published: 19 October 2009 Publication History

Abstract

The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable research attention in recent years. This problem arises in a variety of router management and data streaming applications where large arrays of counters are used to track various network statistics and implement various counting sketches. It proves too costly to store such large counter arrays entirely in SRAM while DRAM is viewed as too slow for providing wirespeed updates at such high speeds.
In this paper, we propose a DRAM-based counter architecture that can effectively maintain wirespeed updates to large counter arrays. The proposed approach is based on the observation that modern commodity DRAM architectures, driven by aggressive performance roadmaps for consumer applications (e.g. video games), have advanced architecture features that can be exploited to make a DRAM-based solution practical. In particular, we propose a randomized DRAM architecture that can harness the performance of modern commodity DRAM offerings by interleaving counter updates to multiple memory banks. The proposed architecture makes use of a simple randomization scheme, a small cache, and small request queues to statistically guarantee a near-perfect load-balancing of counter updates to the DRAM banks. The statistical guarantee of the proposed scheme is proven using a novel combination of convex ordering and large deviation theory. Our proposed counter scheme can support arbitrary increments and decrements at wirespeed, and it can support different number representations, including both integer and floating point number representations.

References

[1]
Intel Lynnfield processor.
[2]
XDR datasheet. Rambus, Inc., 2002--2003.
[3]
XDR-2 datasheet. Rambus, Inc., 2004--2005.
[4]
Intel IXP 2855 network processor product brief. Intel Corporation, 2005.
[5]
A. Cvetkovski. An algorithm for approximate counting using limited memory resources. In ACM Sigmetrics, 2007.
[6]
R. Graham, D. Knuth, and O. Patashnik. Concrete Mathematics: A Foundation for Computer Science. Addison-Wesley, 2nd edition, 1994.
[7]
M. Gschwind, H. P. Hofstee, B. Flachs, M. Hopkins, Y. Watanabe, and T. Yamazaki. Synergistic processing in cell's multicore architecture. IEEE Micro, 26(2):10--24, 2006.
[8]
W. Hoeffding. Probability inequalities for sums of bounded random variables. Journal of the American Statistical Association, 58(301):13--30, 1963.
[9]
S. I. Hong, S. A. McKee, M. H. Salinas, R. H. Klenke, J. H. Aylor, and W. A. Wulf. Access order and effective bandwidth for streams on a direct rambus memory. In IEEE HPCA, page 80, 1999.
[10]
N. Hua, B. Lin, J. Xu, and H. Zhao. BRICK: A novel exact active statistics counter architecture. In ACM/IEEE ANCS, 2008.
[11]
P. Indyk. Stable distributions, pseudorandom generators, embeddings, and data stream computation. In IEEE FOCS, 2000.
[12]
B. Lin and J. Xu. DRAM is plenty fast for wirespeed statistics counting. In ACM HotMetrics, June 2008.
[13]
W. Lin, S. K. Reinhardt, and D. Burger. Reducing DRAM latencies with an integrated memory hierarchy design. In Proc. of IEEE HPCA, page 301, Washington, DC, USA, 2001.
[14]
Y. Lu, A. Montanari, B. Prabhakar, S. Dharmapurikar, and A. Kabbani. Counter braids: A novel counter architecture for per-flow measurement. In ACM SIGMETRICS, 2008.
[15]
A. W. Marshall and I. Olkin. Inequalities: Theory of Majorization and Its Applications. Academic Press, 1979.
[16]
R. Morris. Counting large numbers of events in small registers. Commun. ACM, 21(10), 1978.
[17]
R. Motwani and P. Raghavan. Randomized Algorithms. Cambridge, 1995.
[18]
A. Muller and D. Stoyan. Comparison Methods for Stochastic Models and Risks. Wiley, 2002.
[19]
C. Pandita and S. Meyn. Worst-case large-deviation asymptotics with application to queueing and information theory. Stochastic Processes and their Applications, 116(5):724--756, 2006.
[20]
D. Patterson and J. Hennessy. Computer Architecture: A QuantitativeApproach. Morgan Kaufmann, 2nd edition, 1996.
[21]
S. Ramabhadran and G. Varghese. Efficient implementation of a statistics counter architecture. SIGMETRICS Perform. Eval. Rev., 31(1):261--271, 2003.
[22]
B. R. Rau. Pseudo-randomly interleaved memory. In Proc. 18th Annual International Symposium on Computer Architecture, 1991.
[23]
M. Roeder and B. Lin. Maintaining exact statistics counters with a multi-level counter memory. In IEEE GLOBECOM, volume 2, pages 576--581, Nov - Dec 2004.
[24]
S. M. Ross. Low-Density Parity-Check Codes. Wiley, 2nd Edition, 1995.
[25]
D. Shah, S. Iyer, B. Prahhakar, and N. McKeown. Maintaining statistics counters in router line cards. Micro, IEEE, 22(1):76--81, Jan/Feb 2002.
[26]
G. Shrimali and N. McKeown. Building packet buffers using interleaved memories. In Workshop on High Performance Switching and Routing (HPSR), May 2005.
[27]
R. Stanojevic. Small active counters. In IEEE Infocom, 2007.
[28]
F. Ware and C. Hampel. Improving power and data efficiency with threaded memory modules. In International Conference on Computer Design (ICCD), pages 417--424, Oct. 2006.
[29]
F. A. Ware and C. Hampel. Micro-threaded row and column operations in a dram core. Rambus White Paper, Mar 2005.
[30]
H. Zhao, A. Lall, M. Ogihara, O. Spatscheck, J. Wang, and J. Xu. A data streaming algorithm for estimating entropies of OD flows. In ACM IMC, 2007.
[31]
Q. Zhao, J. Xu, and Z. Liu. Design of a novel statistics counter architecture with optimal space and time efficiency. SIGMETRICS Perform. Eval. Rev., 34(1):323--334, 2006.

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    cover image ACM Conferences
    ANCS '09: Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
    October 2009
    227 pages
    ISBN:9781605586304
    DOI:10.1145/1882486
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    Published: 19 October 2009

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    Author Tags

    1. convex ordering
    2. large deviation theory
    3. majorization
    4. network measurement
    5. statistics counter

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    • (2016)Mean-field-analysis of coding versus replication in cloud storage systemsIEEE INFOCOM 2016 - The 35th Annual IEEE International Conference on Computer Communications10.1109/INFOCOM.2016.7524626(1-9)Online publication date: Apr-2016
    • (2016)CASE: Cache-assisted stretchable estimator for high speed per-flow measurementIEEE INFOCOM 2016 - The 35th Annual IEEE International Conference on Computer Communications10.1109/INFOCOM.2016.7524608(1-9)Online publication date: Apr-2016
    • (2016)A study of personal information in human-chosen passwords and its security implicationsIEEE INFOCOM 2016 - The 35th Annual IEEE International Conference on Computer Communications10.1109/INFOCOM.2016.7524583(1-9)Online publication date: Apr-2016
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    • (2014)Discount counting for fast flow statistics on flow size and flow volumeIEEE/ACM Transactions on Networking10.1109/TNET.2013.227043922:3(970-981)Online publication date: 1-Jun-2014
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    • (2012)Per-flow traffic measurement through randomized counter sharingIEEE/ACM Transactions on Networking10.1109/TNET.2012.219244720:5(1622-1634)Online publication date: 1-Oct-2012
    • (2012)DRAM-based statistics counter array architecture with performance guaranteeIEEE/ACM Transactions on Networking10.1109/TNET.2011.217136020:4(1040-1053)Online publication date: 1-Aug-2012
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