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Logical time: specification vs. implementation

Published: 24 January 2011 Publication History

Abstract

MARTE/CCSL specifications express chronological and causal relations on UML models. In a previous work, we proposed a mechanism to verify Esterel implementations against MARTE/CCSL specifications. The mechanism was thought to be general enough to be extended to other languages. However, preserving the polychronous semantics of CCSL was pretty easy with a synchronous language but is much harder when the target language does not directly support coincidence/simultaneity. We show here how coincidence can be encoded. The process is illustrated using VHDL

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Cited By

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  • (2016)Generation of SystemVerilog Observers from SysML and MARTE/CCSL2016 IEEE 19th International Symposium on Real-Time Distributed Computing (ISORC)10.1109/ISORC.2016.18(61-68)Online publication date: May-2016
  • (2016)Combining SysML and Marte/CCSL to Model Complex Electronic Systems2016 International Conference on Information Systems Engineering (ICISE)10.1109/ICISE.2016.13(12-17)Online publication date: Apr-2016

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Published In

cover image ACM SIGSOFT Software Engineering Notes
ACM SIGSOFT Software Engineering Notes  Volume 36, Issue 1
January 2011
210 pages
ISSN:0163-5948
DOI:10.1145/1921532
Issue’s Table of Contents

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 January 2011
Published in SIGSOFT Volume 36, Issue 1

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View all
  • (2016)Generation of SystemVerilog Observers from SysML and MARTE/CCSL2016 IEEE 19th International Symposium on Real-Time Distributed Computing (ISORC)10.1109/ISORC.2016.18(61-68)Online publication date: May-2016
  • (2016)Combining SysML and Marte/CCSL to Model Complex Electronic Systems2016 International Conference on Information Systems Engineering (ICISE)10.1109/ICISE.2016.13(12-17)Online publication date: Apr-2016

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