Giorgos Dimitrakopoulos
ABSTRACT
Bufferless switches can be an attractive and energy-efficient design option for on-chip networks when network utilization is low and low-latency operation matters the most. However, this promising design option is limited by the complexity of the control logic required to operate a bufferless switch that imposes large delays and limits the clock frequency. Pipelining is not an option in this low-latency environment. In this paper, we propose a new switch allocator for bufferless switches that parallelizes the steps required for achieving a match between requesting inputs and available outputs and offers significantly faster implementations.
- T. Moscibroda and O. Mutlu, "A case for bufferless routing in on-chip networks", ISCA-36, 2009. Google Scholar
Digital Library
- Z. Lu, M. Zhong, and A. Jantsch, "Evaluation of on-chip networks using deflection routing", GLSVLSI-16, 2006. Google ScholarDigital Library
- C. Gomez, M. E. Gomez, P. Lopez, and J. Duato, "Reducing packet dropping in a bufferless NoC", Euro-Par-14, 2008. Google ScholarDigital Library
- M. Hayenga, N. Jerger, and M. Lipasti, "Scarab: A single cycle adaptive routing and bufferless network", MICRO-42, 2009. Google ScholarDigital Library
- K. Goossens and A. Hansson, "The Aethereal Network on Chip after Ten Years: Goals, Evolution, Lessons, and Future", DAC, 2010. Google ScholarDigital Library
- J. Kim. "Low-cost router microarchitecture for on-chip networks", MICRO-42, 2009. Google ScholarDigital Library
- G. Michelogiannakis, D. Sanchez, W. J. Dally, and C. Kozyrakis, "Evaluating bufferless flow-control for on-chip networks", NOCS, 2010. Google ScholarDigital Library
- S. Tota M. R. Casu, and L. Macchiarulo, "Implementation analysis of NoC: a MPSoC trace-driven approach", GLSVLSI-16, 2006. Google ScholarDigital Library
- Z. Hong and R. Sedgewick, "Notes on merging networks", ACM STOC, 1982 Google ScholarDigital Library
- K. Harteros, "Fast Parallel Comparison Circuits for Scheduling", ăTech. Report FORTH-ICS/TR-304, 2002.Google Scholar
- G. Dimitrakopoulos, N. Chrysos and K. Galanopoulos, "Fast arbiters for on-chip network switches", ICCD, 2008.Google ScholarCross Ref
- G. Dimitrakopoulos, "Logic-level implementation of basic switch components", in Designing Network On-Chip Architectures in the Nanoscale Era, Jose Flieh and Davide Bertozzi, Eds., CRC Press, 2010.Google Scholar
- D. Becker and W. Dally, "Allocator implementations for network-on-chip routers", ACM/IEEE SC, 2009. Google ScholarDigital Library
Index Terms
- Switch allocator for bufferless network-on-chip routers
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