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A FPGA implementation of Chen's algorithm

Published:28 January 2011Publication History
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Abstract

This article is devoted to describing an implementation of Chen's algorithm on FPGA. This algorithm allows the computation of minimum distance of cyclic codes. As an application, we determine the minimum distance of quadratic residue codes of length 223.

References

  1. C. Chen. Computer results on the minimum distance of some binary cyclic codes. IEEE Trans. Inf. Theory, IT-16:359--360, 1970.Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. J. Leon. A probabilistic algorithm for computing minimum weights of large error-correcting codes. IEEE Trans. Inf. Theory, IT-34(5):1354--1359, 1988.Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. F. MacWilliams and N. Sloane. The Theory of Error-Correcting Codes. North-Holland, 1978.Google ScholarGoogle Scholar

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  1. A FPGA implementation of Chen's algorithm

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          cover image ACM Communications in Computer Algebra
          ACM Communications in Computer Algebra  Volume 44, Issue 3/4
          September/December 2010
          145 pages
          ISSN:1932-2240
          DOI:10.1145/1940475
          Issue’s Table of Contents

          Copyright © 2011 Authors

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          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 28 January 2011

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