Glitch: the hidden impact of faulty software by Jeff Papows

This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally equivalent ones (called F-Gates) that can be "frozen" by asserting a ...

Much effort has been made to estimate SER (Soft error rate) in combinational logic. However, little of them involve glitch reconvergence. In this paper, we discuss how to estimate SER in combinational logic when considering reconvergence. We present ...