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Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory

Published:05 March 2011Publication History

ABSTRACT

Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such as Sun's prototype Rock processor and AMD's proposed Advanced Synchronization Facility (ASF), can efficiently execute many transactions, but abort in some cases due to various limitations. Hybrid TM systems can use a compatible software TM (STM) in such cases.

We introduce a family of hybrid TMs built using the recent NOrec STM algorithm that, unlike existing hybrid approaches, provide both low overhead on hardware transactions and concurrent execution of hardware and software transactions. We evaluate implementations for Rock and ASF, exploring how the differing HTM designs affect optimization choices. Our investigation yields valuable input for designers of future best-effort HTMs.

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        • Published in

          cover image ACM Conferences
          ASPLOS XVI: Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
          March 2011
          432 pages
          ISBN:9781450302661
          DOI:10.1145/1950365
          • cover image ACM SIGARCH Computer Architecture News
            ACM SIGARCH Computer Architecture News  Volume 39, Issue 1
            ASPLOS '11
            March 2011
            407 pages
            ISSN:0163-5964
            DOI:10.1145/1961295
            Issue’s Table of Contents
          • cover image ACM SIGPLAN Notices
            ACM SIGPLAN Notices  Volume 46, Issue 3
            ASPLOS '11
            March 2011
            407 pages
            ISSN:0362-1340
            EISSN:1558-1160
            DOI:10.1145/1961296
            Issue’s Table of Contents

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          Publication History

          • Published: 5 March 2011

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