Hoang Le
ABSTRACT
Router virtualization has recently gained much interest in the research community. It allows multiple virtual router instances to run on a common physical router platform. The key metrics in designing network virtual routers are: (1) number of supported virtual router instances, (2) total number of prefixes, and (3) ability to quickly update the virtual table. Limited on-chip memory in FPGA leads to the need for memory-efficient merging algorithms. On the other hand, due to high frequency of combined updates from all the virtual routers, the merging algorithms must be highly efficient. Hence, the router must support quick updates. In this paper, we propose a simple merging algorithm whose performance is not sensitive to the number of routing tables considered. The performance solely depends on the total number of prefixes. We also propose a novel scalable, high-throughput linear pipeline architecture for IP-lookup that supports large virtual routing tables and quick non-blocking update. Using a state-of-the-art Field Programmable Gate Array (FPGA) along with external SRAM, the proposed architecture can support up to 16M IPv4 and 880K IPv6 prefixes. Our implementation shows a sustained through-put of 400 million lookups per second, even when external SRAM is used.
- 2-3 Tree {Online}. {http://en.wikipedia.org}.Google Scholar
- Control plane scaling and router virtualization {Online}. {http://www.juniper.net/us/en/local/pdf/whitepapers/2000261-en.pdf}.Google Scholar
- MPLS {Online}. {http://en.wikipedia.org}.Google Scholar
- NetFPGA {Online}. {http://netfpga.org/}.Google Scholar
- RIS RAW DATA {Online}. {http://data.ris.ripe.net}.Google Scholar
- Router virtualization in service providers {Online}. {http://www.cisco.com/en/US/solutions/collateral/ns341/ns524/ns562/ns573/white_paper_c11-512753.pdf}.Google Scholar
- SAMSUNG SRAMs {Online}. {http://www.samsung.com}.Google Scholar
- F. Baboescu, S. Rajgopal, L. Huang, and N. Richardson. Hardware implementation of a tree based IP lookup algorithm for oc-768 and beyond. In Proc. DesignCon '05, pages 290--294, 2005.Google Scholar
- M. Behdadfar, H. Saidi, H. Alaei, and B. Samari. Scalar prefix search - a new route lookup algorithm for next generation internet. In Proc. INFOCOM '09, 2009.Google ScholarCross Ref
- J. Carapinha and J. Jiménez. Network virtualization: a view from the bottom. In VISA '09: Proceedings of the 1st ACM workshop on Virtualized infrastructure systems and architectures, pages 73--80, New York, NY, USA, 2009. ACM. Google ScholarDigital Library
- N. M. K. Chowdhury and R. Boutaba. A survey of network virtualization. Comput. Netw., 54(5):862--876, 2010. Google ScholarDigital Library
- J. Fu and J. Rexford. Efficient ip-address lookup with a shared forwarding table for multiple virtual routers. In CoNEXT '08: Proceedings of the 2008 ACM CoNEXT Conference, pages 1--12, 2008. Google ScholarDigital Library
- T. Ganegedara, W. Jiang, and V. Prasanna. Frug: A benchmark for packet forwarding in future networks. In IPCCC '10: Proceedings of IEEE IPCCC 2010, 2010.Google ScholarCross Ref
- H. Le and V. K. Prasanna. Scalable high throughput and power efficient ip-lookup on fpga. In Proc. FCCM '09, 2009. Google ScholarDigital Library
- R. Morris, E. Kohler, J. Jannotti, and M. F. Kaashoek. The click modular router. SIGOPS Oper. Syst. Rev., 33(5):217--231, 1999. Google ScholarDigital Library
- D. R. Morrison. Patricia - practical algorithm to retrieve information coded in alphanumeric. J. ACM, 15(4):514--534, 1968. Google ScholarDigital Library
- K. Sklower. A tree-based packet routing table for berkeley unix. In Winter Usenix Conf., pages 93--99, 1991.Google Scholar
- H. Song, M. Kodialam, F. Hao, and T. V. Lakshman. Building scalable virtual routers with trie braiding. In INFOCOM'10: Proceedings of the 29th conference on Information communications, pages 1442--1450, Piscataway, NJ, USA, 2010. IEEE Press. Google ScholarDigital Library
- H. Song, M. S. Kodialam, F. Hao, and T. V. Lakshman. Scalable ip lookups using shape graphs. In Proc. ICNP '09, 2009.Google ScholarDigital Library
- V. Srinivasan and G. Varghese. Fast address lookups using controlled prefix expansion. ACM Trans. Comput. Syst., 17:1--40, 1999. Google ScholarDigital Library
- D. Taylor, J. Turner, J. Lockwood, T. Sproull, and D. Parlour. Scalable ip lookup for internet routers. Selected Areas in Communications, IEEE Journal on, 21(4):522--534, may. 2003. Google ScholarDigital Library
- D. Unnikrishnan, R. Vadlamani, Y. Liao, A. Dwaraki, J. Crenne, L. Gao, and R. Tessier. Scalable network virtualization using fpgas. In FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays, pages 219--228, New York, NY, USA, 2010. ACM. Google ScholarDigital Library
- M. Wang, S. Deering, T. Hain, and L. Dunn. Non-random generator for ipv6 tables. In HOTI '04: Proceedings of the High Performance Interconnects, 2004. on Proceedings. 12th Annual IEEE Symposium, pages 35--40, 2004. Google ScholarDigital Library
- Y.-H. E. Yang and V. K. Prasanna. High throughput and large capacity pipelined dynamic search tree on fpga. In Proc. FPGA '10, 2010. Google ScholarDigital Library
Index Terms
- Memory-efficient and scalable virtual routers using FPGA
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