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INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs

Published: 27 March 2011 Publication History

Abstract

Clock power is the major contributor to dynamic power for modern IC design. A conventional single-bit flip-flop cell uses an inverter chain with a high drive strength to drive the clock signal. Clustering such cells and forming a multi-bit flip-flop can share the drive strength, dynamic power, and area of the inverter chain, even can save the clock network power and facilitate the skew control. Hence, in this paper, we focus on multi-bit flip-flop clustering at post-placement to gain these benefits. Utilizing the properties of Manhattan distance and coordinate transformation, we model the problem instance by two interval graphs and use a pair of linear-size sequences as our representation. Without enumerating all compatible combinations, we extract only partial sequences that are necessary to cluster flip-flops at a time, thus leading to an efficient clustering scheme. Moreover, our coordinate transformation brings fast operations to execute our algorithm. Experimental results show the superior efficiency and effectiveness of our algorithm.

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L. Chen, A. Hung, H.-M. Chen, E. Y.-W. Tsai, S.-H. Chen, M.-H. Ku, and C.-C. Chen. Using multi-bit flip-flop for clock power saving by designcompiler. In Proc. SNUG, 2010.
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Cited By

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  • (2016)Analytical Clustering Score with Application to Postplacement Register ClusteringACM Transactions on Design Automation of Electronic Systems10.1145/289475321:3(1-18)Online publication date: 11-May-2016
  • (2015)Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop MergingProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2717767(93-100)Online publication date: 29-Mar-2015
  • (2015)Comparative analysis of power in Adder using single bit and multi-bit fip-flops, controlled by dynamic hardware control circuit2015 International Conference on Computer, Communication and Control (IC4)10.1109/IC4.2015.7375555(1-5)Online publication date: Sep-2015
  • Show More Cited By

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  1. INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs

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      cover image ACM Conferences
      ISPD '11: Proceedings of the 2011 international symposium on Physical design
      March 2011
      192 pages
      ISBN:9781450305501
      DOI:10.1145/1960397
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 27 March 2011

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      Author Tags

      1. clock power
      2. coordinate transformation
      3. interval graph
      4. multi-bit flip-flops
      5. post-placement optimization

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      March 27 - 30, 2011
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      Cited By

      View all
      • (2016)Analytical Clustering Score with Application to Postplacement Register ClusteringACM Transactions on Design Automation of Electronic Systems10.1145/289475321:3(1-18)Online publication date: 11-May-2016
      • (2015)Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop MergingProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2717767(93-100)Online publication date: 29-Mar-2015
      • (2015)Comparative analysis of power in Adder using single bit and multi-bit fip-flops, controlled by dynamic hardware control circuit2015 International Conference on Computer, Communication and Control (IC4)10.1109/IC4.2015.7375555(1-5)Online publication date: Sep-2015
      • (2014)Design Flow for Flip-Flop Grouping in Data-Driven Clock GatingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.225333822:4(771-778)Online publication date: 1-Apr-2014
      • (2014)A high speed proficient power reduction method using clustering based flip flop merging2014 International Conference on Communication and Signal Processing10.1109/ICCSP.2014.6950084(1424-1429)Online publication date: Apr-2014
      • (2014)Power Optimization of Sequential Circuit Based ALU Using Gated Clock & Pulse Enable LogicProceedings of the 2014 International Conference on Computational Intelligence and Communication Networks10.1109/CICN.2014.212(1006-1010)Online publication date: 14-Nov-2014
      • (2014)Using well-solvable minimum cost exact covering for VLSI clock energy minimizationOperations Research Letters10.1016/j.orl.2014.05.01042:5(332-336)Online publication date: 1-Jul-2014
      • (2014)Easy and difficult exact covering problems arising in VLSI power reduction by clock gatingDiscrete Optimization10.1016/j.disopt.2014.08.00414:C(104-110)Online publication date: 1-Nov-2014
      • (2013)Slack budgeting and slack to length converting for multi-bit flip-flop mergingProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485721(1837-1842)Online publication date: 18-Mar-2013
      • (2013)Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimizationACM Transactions on Design Automation of Electronic Systems10.1145/2491477.249148418:3(1-20)Online publication date: 29-Jul-2013
      • Show More Cited By

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