On behalf of the program committee and organizing committees, it is our pleasure to welcome you to the ACM SIGPLAN/SIGBED Conference on Languages Compilers, Tools, and Theory for Embedded Systems - LCTES 2011. By expanding its scope in the direction of theory and foundations, LCTES brings together researchers working on all aspects relevant to embedded systems, providing a great opportunity for networking and cross-fertilization of ideas. For that same reason, this year's conference featured a Research Highlights session. That session allowed authors of mature works to reflect on their experience. This is a common practice in other scientific disciplines and it is our hope that this small experiment made LCTES an even more exciting networking event.
The call for papers attracted 51 submissions from Asia-Pacific, Europe and the Americas. Each submission was reviewed by at least four program committee members. External reviewers joinedthe review process when necessary. An online PC meeting was held over one week (22-28 October 2010) during which all PC members could read, review and discuss all papers with which they had no conflicts of interest. All papers were thoroughly discussed online using the START Conference Manager infrastructure. At the end of the meeting, 17 papers were accepted on topics in multicore scheduling, system software, synchronous software, debugging and tracing, real-time computing, and software optimization. No author names were revealed to the reviewers until after the PC meeting had finished.
Proceeding Downloads
Scheduling of stream-based real-time applications for heterogeneous systems
Designers of mobile devices face the challenge of providing the user with more processing power while increasing battery life. Heterogeneous systems offer some opportunities to solve this challenge. In an heterogeneous system, multiple classes of ...
Static bus schedule aware scratchpad allocation in multiprocessors
Compiler controlled memories or scratchpad memories offer more predictable program execution times than cache memories. Scratchpad memories are often employed in multi-processor system-on-chip (MPSoC) platforms which seek to meet the performance needs ...
Task-level analysis for a language with async/finish parallelism
The task level of a program is the maximum number of tasks that can be available (i.e., not finished nor suspended) simultaneously during its execution for any input data. Static knowledge of the task level is of utmost importance for understanding and ...
A low-cost wear-leveling algorithm for block-mapping solid-state disks
Multilevel flash memory cells double or even triple storage density, producing affordable solid-state disks for end users. However, flash lifetime is becoming a critical issue in the popularity of solid-state disks. Wear-leveling methods can prevent ...
An approach to improving the structure of error-handling code in the linux kernel
The C language does not provide any abstractions for exception handling or other forms of error handling, leaving programmers to devise their own conventions for detecting and handling errors. The Linux coding style guidelines suggest placing error ...
Targeting complex embedded architectures by combining the multicore communications API (mcapi) with compile-time virtualisation
Within the domain of embedded systems, hardware architectures are commonly characterised by application-specific heterogeneity. Systems may contain multiple dissimilar processing elements, non-standard memory architectures, and custom hardware elements. ...
Divide and recycle: types and compilation for a hybrid synchronous language
Hybrid modelers such as Simulink have become corner stones of embedded systems development. They allow both discrete controllers and their continuous environments to be expressed in a single language. Despite the availability of such tools, there remain ...
Static analysis of synchronous programs in signal for efficient design of multi-clocked embedded systems
In this paper, we propose a sound abstraction for an efficient static analysis of synchronous programs describing multi-clock embedded systems in Signal. This abstraction combines the Boolean theory and numeric interval approximation to adequately ...
Synchronous programming of device drivers for global resource control in embedded operating systems
In embedded systems, controlling a shared resource like the bus, or improving a property like power consumption, may be hard to achieve when programming device drivers individually. There is a need for global resource control, taking decisions based on ...
Dependence-based multi-level tracing and replay for wireless sensor networks debugging
Due to resource constraints and unreliable communication, wireless sensor network (WSN) programming and debugging remain to be a challenging task. Runtime errors must be constantly monitored, often by checking for violations of certain invariants. Once ...
Lowering overhead in sampling-based execution monitoring and tracing
Debugging is an important phase in the embedded software development cycle because of its high proportion in the overall cost in the product development. Debugging is difficult for real-time applications as such programs are time-sensitive and must meet ...
Software debugging and testing using the abstract diagnosis theory
In this paper, we present a notion of observability and controllability in the context of software testing and debugging. Our view of observability is based on the ability of developers, testers, and debuggers to trace back a data dependency chain and ...
Cache persistence analysis: a novel approachtheory and practice
To compute a worst-case execution time (WCET) estimate for a program, the architectural effects of the underlying hardware must be modeled. For modern processors this results in the need for a cache and pipeline analysis. The timing-relevant result of ...
Predictable task migration for locked caches in multi-core systems
Locking cache lines in hard real-time systems is a common means of achieving predictability of cache access behavior and tightening as well as reducing worst case execution time, especially in a multitasking environment. However, cache locking poses a ...
Precise and efficient parametric path analysis
Hard real-time systems require tasks to finish in time. To guarantee the timeliness of such a system, static timing analyses derive upper bounds on the worst-case execution time (WCET) of tasks. There are two types of timing analyses: numeric and ...
An instruction-scheduling-aware data partitioning technique for coarse-grained reconfigurable architectures
In this paper, we propose a data partitioning technique for the memory subsystem that consists of a multi-ported scratchpad memory (SPM) unit and a single-ported data cache in coarse-grained reconfigurable arrays (CGRA) architecture. The embedded ...
Global productiveness propagation: a code optimization technique to speculatively prune useless narrow computations
This paper proposes a unique hardware-software collaborative strategy to remove useless work at 16-bit data-width granularity. The underlying motivation is to design a low power execution platform by exploiting 'narrow' computations. The proposal uses a ...
Index Terms
- Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems