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A Performance-Oriented Algorithm with Consideration on Communication Cost for Dynamically Reconfigurable FPGA Partitioning

Published: 01 May 2011 Publication History

Abstract

Dynamically reconfigurable FPGAs (DRFPGAs) have high logic utilization because of time-multiplexed interconnects and logic. In this article, we propose a performance-oriented algorithm for the DRFPGA partitioning problem. This algorithm partitions a given circuit system into stages such that the upper bound of the execution times of subcircuits is minimized. The communication cost is taken into consideration in the process of searching for the optimal solution. A graph is first constructed to represent the precedence constraints and calculate the number of buffers needed in a partitioning. This algorithm includes three phases. The first phase reduces the problem size by clustering the gates into subsystems that have only one output. Such a subsystem has a large number of intraconnections because the fan-outs of all vertices except for the one output are fed to the vertices inside the subsystem. This phase significantly reduces the computational complexity of partitioning. The second phase finds a partition with optimal performance. Finally, the third phase minimizes the communication cost by using an iterative improvement approach. Experimental results based on the Xilinx architecture show that our algorithm yields better partitioning solutions than traditional approaches.

References

[1]
Bhat, N. B., Chaudhary, K., and Kuh, E. S. 1993. Performance-Oriented fully routable dynamic architecture for a field programmable logic device. Tech. rep. UCB/RELM93/42, University of California, Berkeley.
[2]
Brown, J., Chen, D., Eslick, I., Tau, E., and DeHon, A. 1995. DELTA: Prototype for a First-Generation Dynamically Programmable Gate Array. MIT Press, Cambridge, MA.
[3]
Chang, D. and Marek-Sadowska, M. 1997. Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs. In Proceedings of the ACM International Symposium on Field Programmable Gate Arrays. 142--148.
[4]
Chang, D. and Marek-Sadowska, M. 1999. Partitioning sequential circuits on dynamically reconfigurable FPGAs. IEEE Trans. Comput. 48, 6, 565--578.
[5]
Chao, M. C. T., Wu, G. M., Jiang, I. H. R., and Chang, Y. W. 1999. A clustering- and probability-based approach for time-multiplexed FPGA partitioning. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 364--368.
[6]
Chiu, G. R., Singh, D. P., Manohararajah, V., and Brown, S. D. 2006. Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 135--142.
[7]
Cong, J. and Ding, Y. 1994. On area/depth tradeoff in LUT-based FPGA technology mapping. IEEE Trans. VLSI Syst. 2, 2, 137--148.
[8]
Cong, J., Zheng, L., and Bagrodia, R. 1994. Acyclic multi-way partitioning of Boolean networks. In Proceedings of the 31st Annual Conference on Design Automation. 670--675.
[9]
DeHon, A. 1994. DPGA-Coupled microprocessors: Commodity ICs for the early 21st century. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines. 31--39.
[10]
Fujii, T., Furuta, K.-I., Motomura, M., Nomura, M., Mizuno, M., Anjo, K.-I., Wakabayashi, K., Hirota, Y., Nakazawa, Y.-E., Ito, H., and Yamashina, M. 1999. A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture. In Proceedings of the IEEE International Solid-State Circuits Conference. 364--365.
[11]
Jones, D. and Lewis, D. M. 1995. A time-multiplexed FPGA architecture for logic emulation. In Proceedings of the IEEE Custom Integrated Circuits Conference. 495--498.
[12]
Kao, C. C. and Lai, Y. T. 2005. An efficient algorithm for finding the minimal-area FPGA technology mapping. ACM Trans. Des. Autom. Electron. Syst. 10, 1, 168--186.
[13]
Liu, H., and Wong, D. F. 1998. Network flow based circuit partitioning for time-multiplexed FPGAs. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 497--504.
[14]
Mak, W. K. and Young, E. F. Y. 2003. Temporal logic replication for dynamically reconfigurable FPGA partitioning. IEEE Trans. Comput.-Aid. Des. Integ. Circ. Syst. 22, 7, 952--959.
[15]
Pareek, N. K., Patidar, V., and Sud, K. K. 2006. Image encryption using chaotic logistic map. Image Vis. Comput. 24, 926--934.
[16]
Trimberger, S. 1998. Scheduling designs into a time-multiplexed FPGA. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays. 153--160.
[17]
Trimberger, S., Carberry, D., Johnson, A., and Wong, J. 1997. A time-multiplexed FPGA. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines. 22--28.
[18]
Wong, E. S. H., Young, E. F. Y., and Mak, W. K. 2003. Clustering based acyclic multi-way partitioning. In Proceedings of the ACM Great Lakes Symposium on VLSI. 203--206.
[19]
Wu, G. M., Lin, J. M., and Chang, Y. W. 2001. Generic ILP-based approaches for time-multiplexed FPGA partitioning. IEEE Trans. Comput.-Aid. Des. Integ. Circ. Syst. 20, 10, 1266--1274.

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cover image ACM Transactions on Reconfigurable Technology and Systems
ACM Transactions on Reconfigurable Technology and Systems  Volume 4, Issue 2
May 2011
216 pages
ISSN:1936-7406
EISSN:1936-7414
DOI:10.1145/1968502
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 May 2011
Accepted: 01 January 2010
Revised: 01 July 2009
Received: 01 February 2009
Published in TRETS Volume 4, Issue 2

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Author Tags

  1. Dynamically reconfigurable FPGA
  2. partitioning
  3. performance-oriented
  4. reconfigurable computing

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