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Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm

Authors:

Yiding Han,

Koushik Chakraborty,

Sanghamitra Roy,

Vilasita KuntamukkalaAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 16, Issue 3

Article No.: 23, Pages 1 - 21

https://doi.org/10.1145/1970353.1970356

Published: 01 June 2011 Publication History

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Abstract

In this article, we propose a novel floorplanning algorithm for GPUs. Floorplanning is an inherently sequential algorithm, far from the typical programs suitable for Single-Instruction Multiple-Thread (SIMT)-style concurrency in a GPU. We propose a fundamentally different approach of exploring the floorplan solution space, where we evaluate concurrent moves on a given floorplan. We illustrate several performance optimization techniques for this algorithm in GPUs. To improve the solution quality, we present a comprehensive exploration of the design space, including various techniques to adapt the annealing approach in a GPU. Compared to the sequential algorithm, our techniques achieve 6--188X speedup for a range of MCNC and GSRC benchmarks, while delivering comparable or better solution quality.

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Cited By

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Saha SSarkar SPatra RBhattacharjee S(2021)New Sorting Algorithm—RevWay SortComputational Advancement in Communication, Circuits and Systems10.1007/978-981-16-4035-3_18(203-210)Online publication date: 10-Oct-2021
https://doi.org/10.1007/978-981-16-4035-3_18
Al-Kawam AHarmanani H(2015)A Parallel GPU Implementation of the Timber Wolf Placement AlgorithmProceedings of the 2015 12th International Conference on Information Technology - New Generations10.1109/ITNG.2015.144(792-795)Online publication date: 13-Apr-2015
https://dl.acm.org/doi/10.1109/ITNG.2015.144
Wafai MAhmed ZKeller RHolzmann SSander BResch M(2011)Optimization of Industrial Neural Network Simulators for GPGPUsRevised Selected Papers on New Horizons in Web Based Learning - Volume 769710.1007/978-3-662-43454-3_3(21-29)Online publication date: 8-Dec-2011
https://dl.acm.org/doi/10.1007/978-3-662-43454-3_3

Index Terms

Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 16, Issue 3

June 2011

330 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1970353

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 June 2011

Accepted: 01 December 2010

Revised: 01 September 2010

Received: 01 January 2010

Published in TODAES Volume 16, Issue 3

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Saha SSarkar SPatra RBhattacharjee S(2021)New Sorting Algorithm—RevWay SortComputational Advancement in Communication, Circuits and Systems10.1007/978-981-16-4035-3_18(203-210)Online publication date: 10-Oct-2021
https://doi.org/10.1007/978-981-16-4035-3_18
Al-Kawam AHarmanani H(2015)A Parallel GPU Implementation of the Timber Wolf Placement AlgorithmProceedings of the 2015 12th International Conference on Information Technology - New Generations10.1109/ITNG.2015.144(792-795)Online publication date: 13-Apr-2015
https://dl.acm.org/doi/10.1109/ITNG.2015.144
Wafai MAhmed ZKeller RHolzmann SSander BResch M(2011)Optimization of Industrial Neural Network Simulators for GPGPUsRevised Selected Papers on New Horizons in Web Based Learning - Volume 769710.1007/978-3-662-43454-3_3(21-29)Online publication date: 8-Dec-2011
https://dl.acm.org/doi/10.1007/978-3-662-43454-3_3

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A high-throughput DPI engine on GPU via algorithm/implementation co-optimization

Fast floorplanning by look-ahead enabled recursive bipartitioning

Implementation of K-means segmentation algorithm on Intel Xeon Phi and GPU

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