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Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators

Published: 01 June 2011 Publication History

Abstract

We introduce thread warping, a dynamic optimization technique that customizes multicore architectures to a given application by dynamically synthesizing threads into custom accelerator circuits on FPGAs (Field-Programmable Gate Arrays). Thread warping builds upon previous dynamic synthesis techniques for single-threaded applications, enabling dynamic architectural adaptation to different amounts of thread-level parallelism, while also exploiting parallelism within each thread to further improve performance. Furthermore, thread warping maintains the important separation of function from architecture, enabling portability of applications to architectures with different quantities of microprocessors and FPGAs, an advantage not shared by static compilation/synthesis approaches. We introduce an approach consisting of CAD tools and operating system support that enables thread warping on potentially any microprocessor/FPGA architecture. We evaluate thread warping using a simulator for high-performance computing systems with different interconnections in addition to multicore embedded systems having between 4 and 64 ARM11 microprocessors. On average, thread warping achieved approximately 3x speedup compared to a high-performance quad-core Intel Xeon and 109x compared to an embedded system consisting of 4 ARM11 cores, with a size cost approximately equal to 36 ARM11 cores.

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  • (2015)Transparent acceleration of program execution using reconfigurable hardwareProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757061(1066-1071)Online publication date: 9-Mar-2015
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  1. Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators

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      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 16, Issue 3
      June 2011
      330 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/1970353
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 01 June 2011
      Accepted: 01 January 2011
      Revised: 01 August 2009
      Received: 01 February 2009
      Published in TODAES Volume 16, Issue 3

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      Author Tags

      1. FPGA
      2. embedded systems
      3. reconfigurable computing
      4. runtime optimizations
      5. synthesis

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      View all
      • (2015)Transparent acceleration of program execution using reconfigurable hardwareProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757061(1066-1071)Online publication date: 9-Mar-2015
      • (2015)Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions2015 25th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2015.7294022(1-8)Online publication date: Sep-2015
      • (2014)A Reconfigurable Architecture for Binary Acceleration of Loops with Memory AccessesACM Transactions on Reconfigurable Technology and Systems10.1145/26294687:4(1-20)Online publication date: 29-Dec-2014
      • (2014)Trace-Based Reconfigurable Acceleration with Data Cache and External Memory SupportProceedings of the 2014 IEEE International Symposium on Parallel and Distributed Processing with Applications10.1109/ISPA.2014.29(158-165)Online publication date: 26-Aug-2014

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