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Reconfigurable controllers for synchronization via wagging

Published: 02 May 2011 Publication History

Abstract

Synchronization via wagging is a method by which a high bandwidth data signal can be partitioned into several lower bandwidth data signals in order to increase the synchronization time of a master-slave latch configuration, and by consequence the mean time between failure for each of the latches in the lower bandwidth array of devices. Furthermore, reconfigurable controller hardware grants the circuit designer direct control over the synchronization time of the array of master-slave latches via the use of one-hot control codes.
This work assesses the benefits of unified reconfigurable controller designs over brute force methods when accounting for effects such as process variations. The reconfiguration protocol is discussed, and three separate controller implementations for a wagging synchronizer are compared in a UMC 90 nm technology with operational frequencies of 37 GHz, 19 GHz, and 12 GHz and average power consumption between 1.3 ¼W and 7.5 ¼W per cell in the typical case. Furthermore, the area cost of a unified reconfigurable control device is shown to have a linear growth in complexity as compared the exponential growth present when utilizing selective hardware replication of configurable modes. Conclusions are then drawn outlining future directions for research.

References

[1]
Kinniment, D.J. 2007. Synchronization and Arbitration in Digital Systems. John Wiley & Sons Ltd., West Sussex, U.
[2]
Alshaikh, M., Kinniment, D.J., and Yakovlev, A. 2010. A Synchronizer Design Based on Wagging. 22nd IEEE International Conference on Microelectronics, (Dec. 2010.
[3]
Mullins, R., and Moore, S. 2007. Demystifying Data-Driven and Pausible Clocking Schemes. Proceedings of Thirteenth International Symposium on Advanced Research in Asynchronous Circuits and Systems, (Mar. 2007), 175--185. DOI= http://dx.doi.org/10.1109/ASYNC.2007.1.
[4]
Rabaey, J.M., Chandrakasan, A., and Nikolic, B. 2003. Digital Integrated Circuits: A Design Perspective. Prentice Hall, Upper Saddle River, NJ, p. 27--29.
[5]
Muller, D., and Bartky, W. 1959. A theory of asynchronous circuits. Proceedings of an International Symposium on the Theory of Switching, (Apr. 1959), 204--24.
[6]
Bystrov, A., and Yakovlev, A. 2002. Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment. Proceedings of Eighth International Symposium on Asynchronous Circuits and Systems, (Apr. 2002), 127--136. DOI= http://dx.doi.org/10.1109/ASYNC.2002.100030.
[7]
Cortadella, J., Kishinevsky, M., Kondratyev, A., Lavagno, L., and Yakovlev, A. 2002. Logic Synthesis of Asynchronous Controllers and Interfaces. Springer, Berlin, p. 62--73.

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    cover image ACM Conferences
    GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
    May 2011
    496 pages
    ISBN:9781450306676
    DOI:10.1145/1973009
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 02 May 2011

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    Author Tags

    1. combinational
    2. controllers
    3. reconfigurable
    4. sequential
    5. synchronization

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    GLSVLSI '11: Great Lakes Symposium on VLSI 2011
    May 2 - 4, 2011
    Lausanne, Switzerland

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