Redundancy in SAR ADCs

In this paper, we discuss and analyze the effectiveness of redundancy (also known as digital error correction) and its relationship with DAC settling time, comparator delay, digital logic delay and sampling rate in successive-approximation-register (SAR) ADCs. Behavioral models of SAR ADCs are developed that are four orders of magnitude faster than simulations done in FastSPICE, to predict ADC time progression and to quickly identify the maximum sampling rate that can be used in both redundant and non-redundant cases. We show that redundancy does not always improve sampling rate; instead, the maximum sampling rate depends on the relative magnitudes of different ADC delay components. SPICE simulation in a 65nm CMOS process verifies our behavioral simulation results.