Zheng Ding
ABSTRACT
In this paper, we propose a FPGA-based parallel algorithm to compute the transitive closure of the relation matrix on a fixed-size PE array. Experimental results showed that speedup increases with the problem size. The speedup against a single PE is between 11.3 and 195.9. Compared to a general CPU solution, this algorithm achieves acceleration rate of 3.7 and 376 under the worst and best situations, respectively.
- I. Kuon and J. Rose. Measuring the gap between fpgas and asics. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(2): 203--215, 2007. Google Scholar
Digital Library
- S. Warshall. A theorem on boolean matrices. J. ACM, 9(1): 11--12, 1962. Google ScholarDigital Library
Index Terms
- FPGA based parallel transitive closure algorithm
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