research-article

Analog layout retargeting using geometric programming

Authors:

Shaoxi Wang,

Xinzhang Jia,

Arthur B. Yeh,

Lihong ZhangAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 16, Issue 4

Article No.: 50, Pages 1 - 11

https://doi.org/10.1145/2003695.2003710

Published: 27 October 2011 Publication History

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Abstract

To satisfy the requirements of complex and special analog layout constraints, a new analog layout retargeting method is presented in this article. Our approach uses geometric programming (GP) to achieve new technology design rules, implement device symmetry and matching constraints, and manage parasitics optimization. The GP, a class of nonlinear optimization problem, can be transferred or fitted into a convex optimization problem. Therefore, a global optimum solution can be achieved. Moreover, the GP can address problems with large-scale variables and constraints without setting an initialization variable range. To meet the prerequisites of the GP methodology for analog layout automation, we propose three kinds of mathematical transformations, including negative coefficient transformation, fraction transformation, and maximum of posynomial transformation. The efficiency and effectiveness of the proposed algorithm, as compared with the other existing methods, are demonstrated by a basic case-study example: a two-stage Miller-compensated operational amplifier and a single-ended folded cascode operational amplifier.

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Oldja MKim JJeong DHa S(2021)Hierarchical Scheduling of an SDF/L Graph onto Multiple ProcessorsACM Transactions on Design Automation of Electronic Systems10.1145/348946927:3(1-23)Online publication date: 22-Nov-2021
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Jiang WPop PJiang K(2017)Design optimization for security- and safety-critical distributed real-time applicationsMicroprocessors & Microsystems10.1016/j.micpro.2016.08.00252:C(401-415)Online publication date: 1-Jul-2017
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Patan ASantoro AConca PCarapezza GMagna ARomano VNicosia G(2017)Multi-objective optimization and analysis for the design space exploration of analog circuits and solar cellsEngineering Applications of Artificial Intelligence10.1016/j.engappai.2016.08.01062:C(373-383)Online publication date: 1-Jun-2017
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Index Terms

Analog layout retargeting using geometric programming
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Partitioning and floorplanning

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cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 16, Issue 4

October 2011

326 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2003695

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 27 October 2011

Accepted: 01 April 2011

Revised: 01 March 2011

Received: 01 April 2010

Published in TODAES Volume 16, Issue 4

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Oldja MKim JJeong DHa S(2021)Hierarchical Scheduling of an SDF/L Graph onto Multiple ProcessorsACM Transactions on Design Automation of Electronic Systems10.1145/348946927:3(1-23)Online publication date: 22-Nov-2021
https://dl.acm.org/doi/10.1145/3489469
Jiang WPop PJiang K(2017)Design optimization for security- and safety-critical distributed real-time applicationsMicroprocessors & Microsystems10.1016/j.micpro.2016.08.00252:C(401-415)Online publication date: 1-Jul-2017
https://dl.acm.org/doi/10.1016/j.micpro.2016.08.002
Patan ASantoro AConca PCarapezza GMagna ARomano VNicosia G(2017)Multi-objective optimization and analysis for the design space exploration of analog circuits and solar cellsEngineering Applications of Artificial Intelligence10.1016/j.engappai.2016.08.01062:C(373-383)Online publication date: 1-Jun-2017
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Park HMalik ASalcic Z(2015)Scheduling Globally Asynchronous Locally Synchronous Programs for Guaranteed Response TimesACM Transactions on Design Automation of Electronic Systems10.1145/274096120:3(1-25)Online publication date: 24-Jun-2015
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Po-Cheng Pan Ching-Yu Chin Hung-Ming Chen Tung-Chieh Chen Chin-Chieh Lee Jou-Chun Lin (2015)A Fast Prototyping Framework for Analog Layout Migration With Planar PreservationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.241831234:9(1373-1386)Online publication date: 1-Sep-2015
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Elimination of the effect of bottom-plate capacitors in C-2C DAC using a layout technique

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