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Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis

Published: 21 July 2011 Publication History

Abstract

In all application domains of multimedia, communication and network processing where huge amount of data processing at desired performance and power consumption are a mandatory prerequisite for successful functioning; the system architects have to find a design that fulfills the user requirements of the optimization parameters, while minimizing the cost as much as possible. In this paper a novel FPGA based comparative analysis to compare the cost-performance ratio (CPR) of an Application Specific Processor (ASP) with Microblaze soft core RISC processor is proposed. The paper also proposes an exclusive performance assessment between the FPGA based ASP and Microblaze soft core RISC processor embedded in FPGA. The paper also highlights the design processes of a performance optimized power stringent ASP by converting a computation intensive application into an actual Register Transfer Level (RTL) hardware design as well as the Microblaze soft core RISC processor for a same given application. The experimental results of the FPGA based speedup analysis indicated that for 'N' sets of processed data, the application specific processor performs faster than RISC. Further, it was concluded that speedup of ASP increases proportionally with increase in number of processed data. Moreover, the results of CPR comparison indicated that as the number of units of production increases, the value of CPR for the ASP becomes larger compared to CPR of RISC processor.

References

[1]
Anirban Sengupta, Reza Sedaghat and Zhipeng Zeng, "A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective", Microelectronics Reliability Journal, Elsevier Science, Vol. 50, Issue 3, 2010, pp. 424--437.
[2]
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, "Rapid Design Space Exploration for multi parametric optimization of VLSI designs", Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Paris, 2010, pp. 3164--3167.
[3]
E. Ercanli, C. Papachristou "A Register File and Scheduling Model for Application Specific Processor Synthesis", Proceedings of the 33rd ACM IEEE annual Design Automation Conference, United States, 1996, Pages: 35--40.
[4]
Jelena Trajkovic and Daniel D. Gajski, "Custom Processor Core Construction from C Code", 2008 Symposium on Application Specific Processors, 8--9 June 2008, page(s): 1--6
[5]
John L Hennessy and David A Patterson, "Computer Architecture A Quantitative Approach", second edition, Morgan Kaufmann publishers, 1996, pp. 53--57.
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L. Carro, G. A. Pereira, C. Alba, A. Suzim, "System Design using ASIPs," ecbs, pp. 80, IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), 1996.
[7]
S. Kagan Agun, Morris Chang, "Reconfigurable Fast Memory Management System Design for Application Specific Processors," is VLSI, pp. 92, IEEE Computer Society Annual Symposium on VLSI, 2003.

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  1. Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis

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    cover image ACM Conferences
    ACAI '11: Proceedings of the International Conference on Advances in Computing and Artificial Intelligence
    July 2011
    248 pages
    ISBN:9781450306355
    DOI:10.1145/2007052
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 21 July 2011

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    Author Tags

    1. RISC processor
    2. application specific processor
    3. cost performance ratio
    4. power stringent
    5. register transfer level

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