Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs
Authors: 
Alexandre de Morais Amory, Cristiano Lazzari, Marcelo Soares Lubaszewski, 
Fernando Gehm MoraesAuthors Info & Claims
Alexandre de Morais Amory, Cristiano Lazzari, Marcelo Soares Lubaszewski, Fernando Gehm MoraesAuthors Info & ClaimsPages 73 - 78
Abstract
The use of existing Networks-on-Chip (NoCs) for test data transportation has been proposed to avoid conventional dedicated Test Access Mechanism (TAM), improving the modularity of the test architecture. This paper presents a wire length estimation method used to evaluate the cost of dedicated TAMs for NoC-based SoCs early in the design flow. This wire length information (together with test time, power dissipation, among other test metrics) can help the designer to decide the best test architecture (NoC TAM or dedicated TAM) for a given chip. The experimental results demonstrate that dedicated TAMs require, on average, 26% of the global wires, enforcing quantitatively the benefits of NoC TAMs. On the other hand, results can vary depending on the SoC, from 3% to 70%, demonstrating the need of a fast wire length estimation in early stages of design.
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Index Terms
- Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs
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Information
Published In
August 2011
244 pages
ISBN:9781450308281
DOI:10.1145/2020876
- General Chair:
- Antonio Carlos Cavalcanti,
- Program Chairs:
- Elmar Uwe Kurl Melcher,
- Jürgen Becker
Copyright © 2011 ACM.
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New York, NY, United States
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Published: 30 August 2011
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SBCCI '11
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SBCCI '11: 24th Symposium on Integrated Circuits and Systems Design
August 30 - September 2, 2011
João Pessoa, Brazil
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Overall Acceptance Rate 133 of 347 submissions, 38%
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