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A self-tuning hybrid flash translation layer for embedded systems

Published: 16 June 2011 Publication History

Abstract

The paper represents an approach for designing and implementing a hybrid variant of a flash translation layer. The two classic realizations are the page-mapping FTL and the block-mapping FTL. The page-mapping FTL keeps an address table referring each page of the flash memory array, which is very flexible but takes much space in the RAM because it keeps a descriptor for each page. The block-mapping FTL on the other hand keeps an address table of the blocks which takes far less space but its effectiveness is degraded because of the lack of proper addressing scheme and that's why it is not used frequently. In this paper we will expose an algorithm which in a way combines the two classic approaches and thus mitigates the negative impact of the straightforward solutions.

References

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Michael Wu, W. Zwaenepoel. eNVy: a non-volatile main memory storage system, 1994, ISBN:0-89791-660-3
[2]
Chang L., Kuo T. & Lo S. (2004). Real-time garbage collection for flash-memory storage systems of real-time embedded systems. Journal ACM Transactions on Embedded Computing Systems (TECS), Volume 3 Issue 4, November 2004, ISSN: 1539-9087
[3]
Gal E. & Toledo S. (2005). Algorithms and data structures for flash memories. Journal ACM Computing Surveys (CSUR) Volume 37 Issue 2, June 2005, ISSN: 0360-0300
[4]
Jiang A., Mateescu R. et al (2010). Storage Coding for Wear Leveling in Flash Memories. IEEE Transactions on Information Theory, ISSN: 0018-9448
[5]
Lee Y., Jung D. et al (2008). μ-FTL: a memory-efficient flash translation layer supporting multiple mapping granularities. Proceedings of the 8th ACM international conference on Embedded software. ISBN: 978-1-60558-468-3
[6]
Ben-Aroya A. (2006). Competitive Analysis of Flash-Memory Algorithms. Retrived from: www.cs.tau.ac.il/~abrhambe/AviThesis.pdf
[7]
Aayush Gupta, Youngjae Kim Bhuvan Urgaonkar. DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-Level Address Mapping. In Proc. of ASPLOS'09, March 2009
[8]
Hu Yang, Hong Jiang et al. Achieving Page-Mapping FTL Performance at Block-Mapping FTL Cost by Hiding Address Translation, IEEE, 2010

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Published In

cover image ACM Other conferences
CompSysTech '11: Proceedings of the 12th International Conference on Computer Systems and Technologies
June 2011
688 pages
ISBN:9781450309172
DOI:10.1145/2023607
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

  • TELECVB: TELECOMS - Varna, Bulgaria
  • Austrian Comp Soc: Austrian Computer Society
  • BPCSB: BULGARIAN PUBLISHING COMPANY - Sofia, Bulgaria
  • IOMAIBB: INSTITUTE OF MATHEMATICS AND INFORMATICS - BAS, Bulgaria
  • NBUBB: New Bulgarian University - BAS, Bulgaria
  • Technical University of Sofia
  • IOIACTBB: INSTITUTE OF INFORMATION AND COMMUNICATION TECHNOLOGIES - BAS, Bulgaria
  • TSFPS: THE SEVENTH FRAMEWORK PROGRAMME - SISTER
  • ERSVB: EURORISC SYSTEMS - Varna, Bulgaria
  • FOSEUB: FEDERATION OF THE SCIENTIFIC ENGINEERING UNIONS - Bulgaria
  • UORB: University of Ruse, Bulgaria
  • BBPSB: BULGARIAN BUSINESS PUBLICATIONS - Sofia, Bulgaria
  • CASTUVTB: CYRIL AND ST. METHODIUS UNIVERSITY of Veliko Tarnovo, Bulgaria
  • TECHUVB: Technical University of Varna, Bulgaria
  • LLLPET: LIFELONG LEARNING PROGRAMME - ETN TRICE
  • IEEEBSB: IEEE Bulgaria Section, Bulgaria

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 16 June 2011

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Author Tags

  1. FTL
  2. SSD
  3. address translation
  4. algorithm
  5. block
  6. cache
  7. design
  8. erase
  9. file system
  10. flash
  11. garbage collection
  12. page

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  • Research-article

Conference

CompSysTech '11
Sponsor:
  • TELECVB
  • Austrian Comp Soc
  • BPCSB
  • IOMAIBB
  • NBUBB
  • IOIACTBB
  • TSFPS
  • ERSVB
  • FOSEUB
  • UORB
  • BBPSB
  • CASTUVTB
  • TECHUVB
  • LLLPET
  • IEEEBSB

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Overall Acceptance Rate 241 of 492 submissions, 49%

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