research-article

MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems

Authors:

Yong GuanAuthors Info & Claims

DAC '11: Proceedings of the 48th Design Automation Conference

Pages 17 - 22

https://doi.org/10.1145/2024724.2024730

Published: 05 June 2011 Publication History

Abstract

The new write constraints of multi-level cell (MLC) NAND flash memory make most of the existing flash translation layer (FTL) schemes inefficient or inapplicable. In this paper, we solve several fundamental problems in the design of MLC flash translation layer. The objective is to reduce the garbage collection overhead so as to reduce the average system response time. We make the key observation that the valid page copy is the essential garbage collection overhead. Based on this observation, we propose two approaches, namely, concentrated mapping and postponed reclamation, to effective reduce the valid page copies. We conduct experiments on a set of benchmarks from both the real world and synthetic traces. The experimental results show that our scheme can achieve a significant reduction in the average system response time compared with the previous work.

References

[1]

OLTP trace from umass trace repository. http://traces.cs.umass.edu/index.php/Storage/Storage.

[2]

Samsung Electronics. K9LBG08U0M(v1.0)-32GB DDP MLC data sheet. http://www.samsung.com.

[3]

Samsung Electronics. Page program addressing for MLC NAND application note. http://www.samsung.com, 2009.

[4]

A. Ban. Flash file system. US patent 5,404,485, 1995.

[5]

A. Ban. Flash-memory translation layer for NAND flash (NFTL). M-systems, 1998.

[6]

Y.-H. Chang and T.-W. Kuo. A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems. In DAC'09, pages 858--863, 2009.

Digital Library

[7]

H. Cho, D. Shin, and Y. I. Eom. KAST: K-associative sector translation for NAND flash memory in real-time systems. In DATE'09, pages 507--512, 2009.

Digital Library

[8]

S. Choudhuri and T. Givargis. Deterministic service guarantees for NAND flash using partial block cleaning. In CODES+ISSS'08, pages 19--24, 2008.

Digital Library

[9]

A. Gupta, Y. Kim, and B. Urgaonkar. DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings. In ASPLOS'09, pages 229--240, 2009.

Digital Library

[10]

J.-U. Kang, H. Jo, J.-S. Kim, and J. Lee. A superblock based flash translation layer for NAND flash memory. In EMSOFT'06, pages 161--170, 2006.

Digital Library

[11]

S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song. A log buffer-based flash translation layer using fully-associative sector translation. TECS, 6(3):18, 2007.

Digital Library

[12]

C. Park, W. Cheon, J. Kang, K. Roh, W. Cho, and J.-S. Kim. A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications. TECS, 7(4):1--23, 2008.

Digital Library

[13]

Z. Qin, Y. Wang, D. Liu, and Z. Shao. Demand-based block-level address mapping in large-scale NAND flash storage systems. In CODES+ISSS'10, pages 173--182, 2010.

Digital Library

[14]

Y. Wang, D. Liu, M. Wang, Z. Qin, Z. Shao, and Y. Guan. RNFTL: a reuse-aware NAND flash translation layer for flash memory. In LCTES'10, pages 163--172, 2010.

Digital Library

[15]

C.-H. Wu and T.-W. Kuo. An adaptive two-level management for the flash translation layer in embedded systems. In ICCAD'06, pages 601--606, 2006.

Digital Library

Cited By

Wang WHo CLi YChen LChang Y(2023)Reaping Both Latency and Reliability Benefits With Elaborate Sanitization Design for 3D TLC NAND FlashIEEE Transactions on Computers10.1109/TC.2023.327228072:11(3029-3041)Online publication date: Nov-2023
https://doi.org/10.1109/TC.2023.3272280
Chang YHo CTsao CLiao SWang WKuo TChang YHong JBures MPark JCerny T(2022)On enduring more data through enabling page rewrite capability on multi-level-cell flash memoryProceedings of the 37th ACM/SIGAPP Symposium on Applied Computing10.1145/3477314.3507088(107-115)Online publication date: 25-Apr-2022
https://dl.acm.org/doi/10.1145/3477314.3507088
Park SLee J(2021)Analysis of the K2 Scheduler for a Real-Time System with an SSDElectronics10.3390/electronics1007086510:7(865)Online publication date: 6-Apr-2021
https://doi.org/10.3390/electronics10070865
Show More Cited By

Index Terms

MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems
1. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Memory management
        Secondary storage

Recommendations

MNFTL: An Efficient Flash Translation Layer for MLC NAND Flash Memory

The write constraints of Multi-Level Cell (MLC) NAND flash memory make most of the existing flash translation layer (FTL) schemes inefficient or inapplicable. In this article, we solve several fundamental problems in the design of MLC flash translation ...
LazyFTL: a page-level flash translation layer optimized for NAND flash memory
SIGMOD '11: Proceedings of the 2011 ACM SIGMOD International Conference on Management of data

Flash is a type of electronically erasable programmable read-only memory (EEPROM), which has many advantages over traditional magnetic disks, such as lower access latency, lower power consumption, lack of noise, and shock resistance. However, due to its ...
Exploiting Sequential and Temporal Localities to Improve Performance of NAND Flash-Based SSDs

NAND flash-based Solid-State Drives (SSDs) are becoming a viable alternative as a secondary storage solution for many computing systems. Since the physical characteristics of NAND flash memory are different from conventional Hard-Disk Drives (HDDs), ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '11: Proceedings of the 48th Design Automation Conference

June 2011

1055 pages

ISBN:9781450306362

DOI:10.1145/2024724

General Chair:
Leon Stok
IBM Corp., Hopewell Jct., NY
,
Program Chairs:
Nikil Dutt
Univ. of California, Irvine, CA
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE Council on Electronic Design Automation (CEDA)

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2011

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

Research Grants Council, University Grants Committee, Hong Kong

Conference

DAC '11

Sponsor:

EDAC
SIGDA

DAC '11: The 48th Annual Design Automation Conference 2011

June 5 - 10, 2011

California, San Diego

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

98
Total Citations
View Citations
637
Total Downloads

Downloads (Last 12 months)11
Downloads (Last 6 weeks)2

Reflects downloads up to 05 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Wang WHo CLi YChen LChang Y(2023)Reaping Both Latency and Reliability Benefits With Elaborate Sanitization Design for 3D TLC NAND FlashIEEE Transactions on Computers10.1109/TC.2023.327228072:11(3029-3041)Online publication date: Nov-2023
https://doi.org/10.1109/TC.2023.3272280
Chang YHo CTsao CLiao SWang WKuo TChang YHong JBures MPark JCerny T(2022)On enduring more data through enabling page rewrite capability on multi-level-cell flash memoryProceedings of the 37th ACM/SIGAPP Symposium on Applied Computing10.1145/3477314.3507088(107-115)Online publication date: 25-Apr-2022
https://dl.acm.org/doi/10.1145/3477314.3507088
Park SLee J(2021)Analysis of the K2 Scheduler for a Real-Time System with an SSDElectronics10.3390/electronics1007086510:7(865)Online publication date: 6-Apr-2021
https://doi.org/10.3390/electronics10070865
Yang MWu CChen SLin YChang CChang Y(2021)On Minimizing Internal Data Migrations of Flash Devices via Lifetime-Retention HarmonizationIEEE Transactions on Computers10.1109/TC.2020.298955470:3(428-439)Online publication date: 1-Mar-2021
https://doi.org/10.1109/TC.2020.2989554
Ma CWang YShen ZChen RWang ZShao Z(2020)MNFTLACM Transactions on Design Automation of Electronic Systems10.1145/339803725:6(1-19)Online publication date: 12-Aug-2020
https://dl.acm.org/doi/10.1145/3398037
Chen STsao CChang Y(2020)Beyond Address Mapping: A User-Oriented Multiregional Space Management Design for 3-D NAND Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.291293739:6(1286-1299)Online publication date: Jun-2020
https://doi.org/10.1109/TCAD.2019.2912937
Feng YFeng DTong WLiu JLi S(2020)Multiple Subpage Writing FTL in MLC by Exploiting Dual Mode OperationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.289068939:3(599-612)Online publication date: Mar-2020
https://doi.org/10.1109/TCAD.2018.2890689
Yang MChang YKuo TWu C(2020)Request Flow Coordination for Growing-Scale Solid-State DrivesIEEE Transactions on Computers10.1109/TC.2020.296843969:6(832-843)Online publication date: 1-Jun-2020
https://doi.org/10.1109/TC.2020.2968439
Kishani MAhmadian SAsadi H(2020)A Modeling Framework for Reliability of Erasure Codes in SSD ArraysIEEE Transactions on Computers10.1109/TC.2019.296269169:5(649-665)Online publication date: 1-May-2020
https://doi.org/10.1109/TC.2019.2962691
Yu DHsieh J(2020)A Management Scheme of Multi-Level Retention-Time Queues for Improving the Endurance of Flash-Memory Storage DevicesIEEE Transactions on Computers10.1109/TC.2019.295439869:4(549-562)Online publication date: 1-Apr-2020
https://doi.org/10.1109/TC.2019.2954398
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten