3D heterogeneous system integration: application driver for 3D technology development

Three dimensional integration complements semiconductor scaling; it enables a higher integration density as well as heterogeneous technology integration. Using 3D chip stacking, it is possible to extend the number of functions per 3D chip well beyond the near-term capabilities of traditional scaling. The 3D strata may be realized using advanced CMOS technology nodes but may also exploit a wide variety of device technologies to optimize system performance.

3D of electronic circuits has become a field of great interest in the microelectronics community. A wide variety of approaches are being proposed for an equally wide variety of applications. These approaches can be categorized based on their intersection with the interconnect hierarchy on chip and in the package: from local-to-global interconnect, to bond-pad-level, package and board level. This paper will focus on 3D interconnects using through-Si-vias that allow interconnectivity at the on-chip global interconnect level. The physical dimensions of these TSVs are 5μm diameter and are 50μm deep and can be placed at a minimum pitch of 10μm.

The study and development of 3D System integration requires a concurrent exploration of technology and design. This is particularly the case when considering heterogeneous systems, exploiting different technologies that cannot be integrated in a single IC process. 3D-technology with high density TSV's allow for the seamless integration of circuit blocks (IP blocks) of different technologies in the same manner as a traditional SOC architecture, resulting in a 3D-SOC implementation: concurrently designed IC's in heterogeneous technologies.

The 3D integration approach should be cost-effective and consider the potential compound yield risks by adopting the appropriate testing and known-good-die strategies. A path finding design flow for 3D has been implemented that enables the study the system-level trade-offs at an early phase of the system design. In this path finding design flow, the physical characteristics of a 3D stacked circuit implementation are accounted for. This includes detailed electrical models for the TSV and μbump interconnections, compact mechanical models that account for the impact of mechanical stresses inducted buy the TSV on neighboring components, mechanical stresses imposed by the package and compact thermal models that allow for a fast estimation of chip temperatures across the die within a 3D-stack.