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Significance driven computation on next-generation unreliable platforms

Published: 05 June 2011 Publication History

Abstract

In this paper, we propose a design paradigm for energy efficient and variation-aware operation of next-generation multicore heterogeneous platforms. The main idea behind the proposed approach lies on the observation that not all operations are equally important in shaping the output quality of various applications and of the overall system. Based on such an observation, we suggest that all levels of the software design stack, including the programming model, compiler, operating system (OS) and runtime system should identify the critical tasks and ensure correct operation of such tasks by assigning them to dynamically adjusted reliable cores/units. Specifically, based on error rates and operating conditions identified by a sense-and-adapt (SeA) unit, the OS selects and sets the right mode of operation of the overall system. The run-time system identifies the critical/less-critical tasks based on special directives and schedules them to the appropriate units that are dynamically adjusted for highly-accurate/approximate operation by tuning their voltage/frequency. Units that execute less significant operations can operate at voltages less than what is required for correct operation and consume less power, if required, since such tasks do not need to be always exact as opposed to the critical ones. Such scheme can lead to energy efficient and reliable operation, while reducing the design cost and overheads of conventional circuit/micro-architecture level techniques.

References

[1]
S. Borkar et. al., "Designing reliable systems from unreliable components: The challenges of transistor variability and degradation," IEEE Micro, 2005, pp. 10--16.
[2]
Dan Ernst, et al., "Razor: Circuit-Level Correction of Timing Errors for Low- Power Operation," IEEE Micro, 2004, pp.10--20.
[3]
B. Shim, et al., "Reliable Low-Power Digital Signal Processing via Reduced Precision Redundancy," IEEE TVLSI, 2004, pp. 497--510.
[4]
L. Leem, et al., "ERSA: Error-Resilient System Architecture for Probabilistic Applications," IEEE DATE, 2010.
[5]
G. Karakonstantis, et al., "System Level DSP Synthesis Using Voltage Overscaling, Unequal Error Protection & Adaptive Quality Tuning," IEEE SiPS, 2009.

Cited By

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  • (2017)Runtime Slack Creation for Processor Performance Variability using System ScenariosACM Transactions on Design Automation of Electronic Systems10.1145/315215823:2(1-23)Online publication date: 21-Dec-2017
  • (2017)On resilient task allocation and scheduling with uncertain quality checkers2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2017.7858357(408-413)Online publication date: Jan-2017
  • (2016)ApproxMap: On task allocation and scheduling for resilient applications2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2016.7428031(318-323)Online publication date: Jan-2016

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cover image ACM Conferences
DAC '11: Proceedings of the 48th Design Automation Conference
June 2011
1055 pages
ISBN:9781450306362
DOI:10.1145/2024724

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2011

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Author Tags

  1. approximate computing
  2. energy efficient
  3. software

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all
  • (2017)Runtime Slack Creation for Processor Performance Variability using System ScenariosACM Transactions on Design Automation of Electronic Systems10.1145/315215823:2(1-23)Online publication date: 21-Dec-2017
  • (2017)On resilient task allocation and scheduling with uncertain quality checkers2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2017.7858357(408-413)Online publication date: Jan-2017
  • (2016)ApproxMap: On task allocation and scheduling for resilient applications2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2016.7428031(318-323)Online publication date: Jan-2016

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