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MUSTARD: a coupled, stochastic/deterministic, discrete/continuous technique for predicting the impact of random telegraph noise on SRAMs and DRAMs

Published: 05 June 2011 Publication History

Abstract

With aggressive technology scaling and heightened variability, SRAMs and DRAMs have become vulnerable to Random Telegraph Noise (RTN). The bias-dependent, random temporal nature of RTN presents significant challenges to understanding its effects on circuits. In this paper, we propose MUSTARD, a technique and tool for predicting the impact of RTN on SRAMs/DRAMs in the presence of variability. MUSTARD enables accurate, non-stationary, two-way-coupled, discrete stochastic RTN simulation seamlessly integrated with deterministic, continuous circuit simulation. Using MUSTARD, we are able to predict experimentally observed RTN-induced failures in SRAMs, and generate statistical characterisations of bit errors in SRAMs and DRAMs. We also present MUSTARD-generated results showing the effect of RTN on DRAM retention times.

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      cover image ACM Conferences
      DAC '11: Proceedings of the 48th Design Automation Conference
      June 2011
      1055 pages
      ISBN:9781450306362
      DOI:10.1145/2024724
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      Published: 05 June 2011

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      Author Tags

      1. SRAM/DRAM design
      2. circuit simulation
      3. random telegraph noise

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      • (2023)Investigation of the Off-State Degradation in Advanced FinFET Technology—Part II: Compact Aging Model and Impact on CircuitsIEEE Transactions on Electron Devices10.1109/TED.2023.323958770:3(921-927)Online publication date: Mar-2023
      • (2023)Investigation of the Off-State Degradation in Advanced FinFET Technology—Part I: Experiments and AnalysisIEEE Transactions on Electron Devices10.1109/TED.2023.323958570:3(914-920)Online publication date: Mar-2023
      • (2020)Measurement and Simulation Methods for Assessing SRAM Reliability Against Random Telegraph NoiseNoise in Nanoscale Semiconductor Devices10.1007/978-3-030-37500-3_8(259-284)Online publication date: 27-Apr-2020
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      • (2017)How close to the CMOS voltage scaling limit for FinFET technology? — Near-threshold computing and stochastic computing2017 IEEE 12th International Conference on ASIC (ASICON)10.1109/ASICON.2017.8252410(56-59)Online publication date: Oct-2017
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