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Fast and accurate source-level simulation of software timing considering complex code optimizations

Published: 05 June 2011 Publication History

Abstract

This paper presents an approach for accurately estimating the execution time of parallel software components in complex embedded systems. Timing annotations obtained from highly optimized binary code are added to the source code of software components which is then integrated into a SystemC transaction-level simulation. This approach allows a fast evaluation of software execution times while being as accurate as conventional instruction set simulators. By simulating binary-level control flow in parallel to the original functionality of the software, even compiler optimizations heavily modifying the structure of the generated code can be modeled accurately. Experimental results show that the presented method produces timing estimates within the same level of accuracy as an established commercial tool for cycle-accurate instruction set simulation while being at least 20 times faster.

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  • (2021)Software-defined Temporal Decoupling in Virtual Platforms2021 IEEE 34th International System-on-Chip Conference (SOCC)10.1109/SOCC52499.2021.9739242(40-45)Online publication date: 14-Sep-2021
  • (2020)A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCsInternational Journal of Parallel Programming10.1007/s10766-020-00656-0Online publication date: 5-Mar-2020
  • (2019)WCET Analysis meets Virtual PrototypingProceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems10.1145/3323439.3323978(13-22)Online publication date: 27-May-2019
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        cover image ACM Conferences
        DAC '11: Proceedings of the 48th Design Automation Conference
        June 2011
        1055 pages
        ISBN:9781450306362
        DOI:10.1145/2024724
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Published: 05 June 2011

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        Author Tags

        1. software timing simulation
        2. virtual prototypes

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        Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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        View all
        • (2021)Software-defined Temporal Decoupling in Virtual Platforms2021 IEEE 34th International System-on-Chip Conference (SOCC)10.1109/SOCC52499.2021.9739242(40-45)Online publication date: 14-Sep-2021
        • (2020)A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCsInternational Journal of Parallel Programming10.1007/s10766-020-00656-0Online publication date: 5-Mar-2020
        • (2019)WCET Analysis meets Virtual PrototypingProceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems10.1145/3323439.3323978(13-22)Online publication date: 27-May-2019
        • (2019)SIMULTimeProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287625(526-531)Online publication date: 21-Jan-2019
        • (2019)Accelerating Host-Compiled Simulation by Modifying IR Code: Industrial application in the spatial domain2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS)10.1109/DCIS201949030.2019.8959846(1-6)Online publication date: Nov-2019
        • (2019)InvadeSIM-A Simulation Framework for Invasive Parallel Programs and ArchitecturesModeling and Simulation of Invasive Applications and Architectures10.1007/978-981-13-8387-8_3(41-76)Online publication date: 31-May-2019
        • (2018)A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimationProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201717(452-457)Online publication date: 22-Jan-2018
        • (2018)An Integration Flow for Mixed-Critical Embedded Systems on a Flexible Time-Triggered PlatformACM Transactions on Design Automation of Electronic Systems10.1145/319083723:4(1-25)Online publication date: 9-May-2018
        • (2018)A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimation2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297365(452-457)Online publication date: Jan-2018
        • (2018)Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight TablesSystem Level Design from HW/SW to Memory for Embedded Systems10.1007/978-3-319-90023-0_16(197-209)Online publication date: 17-Apr-2018
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