skip to main content
10.1145/2024724.2024863acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

Dynamic effort scaling: managing the quality-efficiency tradeoff

Published: 05 June 2011 Publication History

Abstract

Several recently proposed design techniques leverage the inherent error resilience of applications for improved efficiency (energy or performance). Hardware and software systems that are thus designed may be viewed as "scalable effort systems", since they offer the capability to modulate the effort that they expend towards computation, thereby allowing for tradeoffs between output quality and efficiency.
We propose the concept of Dynamic Effort Scaling (DES), which refers to dynamic management of the control knobs that are exposed by scalable effort systems. We argue the need for DES by observing that the degree of resilience often varies significantly across applications, across datasets, and even within a dataset. We propose a general conceptual framework for DES by formulating it as a feedback control problem, wherein the scaling mechanisms are regulated with the goal of maintaining output quality within a certain specified limit. We present an implementation of Dynamic Effort Scaling in the context of a scalable-effort processor for Support Vector Machines, and evaluate it under various application scenarios and data sets. Our results clearly demonstrate the benefits of the proposed approach --- statically setting the scaling mechanisms leads to either significant error overshoot or significant opportunities for energy savings left on the table unexploited. In contrast, DES is able to effectively regulate the output quality while maximally exploiting the time-varying resiliency in the workload.

References

[1]
V. Wong and M. Horowitz. Soft error resilience of probabilistic inference applications. In Proc. SELSE, 2006.
[2]
N. R. Shanbhag, R. A. Abdallah, R. Kumar, and D. L. Jones. Stochastic computation. In Proc. DAC, pages 859--864, 2010.
[3]
S. T. Chakradhar and A. Raghunathan. Best-effort Computing: Re-thinking Parallel Software and Hardware. In Proc. DAC, pages 865--870, 2010.
[4]
M. A. Breuer. Hardware that produces bounded rather than exact results. In Proc. DAC, pages 871--876, 2010.
[5]
A. P. Chandrakasan and R. W. Brodersen, editors. Low-Power CMOS Design. Wiley-IEEE Press, 1st edition, 1997.
[6]
L. Benini and G. DeMicheli. Dynamic Power Management: Design Techniques and CAD Tools. Kluwer Academic Publishers, Norwell, MA, USA, 1998.
[7]
R. Hegde and N. R. Shanbhag. Energy-efficient signal processing via algorithmic noise-tolerance. In Proc. ISLPED, pages 30--35, 1999.
[8]
Naresh Shanbhag. Reliable and energy-efficient digital signal processing. In Proc. DAC, pages 830--835, 2002.
[9]
R. Hegde and N. R. Shanbhag. A low-power digital filter IC via soft DSP. In Proc. CICC, pages 309--312, 2001.
[10]
G. V. Varatkar and N. R. Shanbhag. Error-resilient motion estimation architecture. IEEE Trans. VLSI Systems, 16(10):1399--1412, 2008.
[11]
Tong-Yu Hsieh, Kuen-Jong Lee, and M. A. Breuer. An error rate based test methodology to support error-tolerance. Reliability, IEEE Transactions on, 57(1):204--214, 2008.
[12]
Z. Jiang and S. K. Gupta. An ATPG for threshold testing: Obtaining acceptable yield in future processes. In Proc. ITC, pages 824--833, 2002.
[13]
K. V. Palem. Energy aware algorithm design via probabilistic computing: From algorithms and models to Moore's law and novel (semiconductor) devices. In Proc. CASES, pages 113--116, 2003.
[14]
K. V. Palem, N. B. Chakrapani, Z. M. Kedem, A. Lingamneni, and K. K. Muntimadugu. Sustaining Moore's law in embedded computing through probabilistic and approximate design: Retrospects and prospects. In Proc. CASES, pages 1--10, 2009.
[15]
D. Mohapatra, G. Karakonstantis, and K. Roy. Significance driven computation: A voltage-scalable, variation-aware, quality-tuning motion estimator. In Proc. ISLPED, pages 195--200, 2009.
[16]
V. K. Chippa, D. Mohapatra, A. Raghunathan, K. Roy, and S. T. Chakradhar. Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency. In Proc. DAC, pages 555--560, 2010.
[17]
L. Leem, H. Cho, J. Bau, Q. A. Jacobson, and S. Mitra. ERSA: Error resilient system architecture for probabilistic applications. In Proc. DATE, pages 1560--1565, 2010.
[18]
W. Baek and T. M. Chilimbi. Green: A framework for supporting energy-conscious programming using controlled approximation. Proc. PLDI, pages 198--209, 2010.
[19]
Y. V. Ivanov and C. J. Bleakley. Dynamic complexity scaling for real-time H.264/AVC video encoding. In Proc. MULTIMEDIA, pages 962--970, 2007.
[20]
M. Shafique, L. Bauer, and J. Henkel. enBudget: A run-time adaptive predictive energy-budgeting scheme for energy-aware motion estimation in H.264/MPEG-4 AVC video encoder. In Proc. DATE, pages 1725--1730, 2010.
[21]
V. N. Vapnik. The nature of statistical learning theory. Springer-Verlag New York, Inc., New York, NY, USA, 1995.
[22]
Mohapatra Debabrata, Chippa Vinay, Raghunathan Anand, and Roy and Kaushik. Design of voltage scalable metafunctions for multimedia, recoginition and mining applications. In DATE, 2011.
[23]
D. Ernst et al. Razor: A low-power pipeline based on circuit-level timing speculation. In Proc. MICRO, pages 7--18, 2003.
[24]
K. J. Astrom and T. Hagglund, editors. PID Controllers: Theory, Design, and Tuning. ISA, 2nd edition, 1995.
[25]
J. Park, D. Shin, N. Chang, and M. Pedram. Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors. In Proc. ISLPED, pages 419--424, 2010.
[26]
Milde. www.nec-labs.com.

Cited By

View all
  • (2021)Multiple approximate instances in neural processing units for energy-efficient circuit synthesisProceedings of the 2021 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems10.1145/3451939.3477594(3-5)Online publication date: 30-Sep-2021
  • (2021)Cross-Layer Approximate Hardware Synthesis for Runtime Configurable AccuracyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.306831229:6(1231-1243)Online publication date: Jun-2021
  • (2021)On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-ChipIEEE Transactions on Computers10.1109/TC.2020.302718270:11(1817-1830)Online publication date: 1-Nov-2021
  • Show More Cited By

Index Terms

  1. Dynamic effort scaling: managing the quality-efficiency tradeoff

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    DAC '11: Proceedings of the 48th Design Automation Conference
    June 2011
    1055 pages
    ISBN:9781450306362
    DOI:10.1145/2024724
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 05 June 2011

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. approximate computing
    2. dynamic effort scaling
    3. low power design
    4. mining
    5. recognition
    6. scalable effort
    7. support vector machines

    Qualifiers

    • Research-article

    Funding Sources

    Conference

    DAC '11
    Sponsor:

    Acceptance Rates

    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

    Upcoming Conference

    DAC '25
    62nd ACM/IEEE Design Automation Conference
    June 22 - 26, 2025
    San Francisco , CA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)11
    • Downloads (Last 6 weeks)6
    Reflects downloads up to 28 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2021)Multiple approximate instances in neural processing units for energy-efficient circuit synthesisProceedings of the 2021 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems10.1145/3451939.3477594(3-5)Online publication date: 30-Sep-2021
    • (2021)Cross-Layer Approximate Hardware Synthesis for Runtime Configurable AccuracyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.306831229:6(1231-1243)Online publication date: Jun-2021
    • (2021)On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-ChipIEEE Transactions on Computers10.1109/TC.2020.302718270:11(1817-1830)Online publication date: 1-Nov-2021
    • (2020)HEAP: A Holistic Error Assessment Framework for Multiple Approximations Using Probabilistic Graphical ModelsElectronics10.3390/electronics90203739:2(373)Online publication date: 22-Feb-2020
    • (2020)Runtime Accuracy-Configurable Approximate Hardware Synthesis Using Logic Gating and Relaxation2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116272(1578-1581)Online publication date: Mar-2020
    • (2020)Exploiting Errors for EfficiencyACM Computing Surveys10.1145/339489853:3(1-39)Online publication date: 12-Jun-2020
    • (2020)Logic Synthesis of Approximate CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.294068039:10(2503-2515)Online publication date: Oct-2020
    • (2019)Algorithmic-Level Approximate Computing Applied to Energy Efficient HEVC DecodingIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2016.25936447:1(5-17)Online publication date: 1-Jan-2019
    • (2019)Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications2019 IEEE Custom Integrated Circuits Conference (CICC)10.1109/CICC.2019.8780323(1-4)Online publication date: Apr-2019
    • (2018)Efficient synthesis of approximate threshold logic circuits with an error rate guarantee2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342111(773-778)Online publication date: Mar-2018
    • Show More Cited By

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media