Byungchul Hong
ABSTRACT
When designing an SoC (system-on-chip), one should ensure that the chip's architecture delivers optimal data throughput for high-speed connectivity blocks on practical use, taking of several layers of software into account. Previous works such as simulation based estimation method or analytical method that focused on estimation of low level throughput in link layer are not adequate for accurately estimating throughput of the real silicon SoC because practical use cases of such complex connectivity blocks typically require extensive software operation on top of platform operating systems like Linux. FPGA-based emulation, therefore, is commonly used to verify functional correctness of complex connectivity blocks in a more realistic usage scenario with real connectivity devices like USB 2.0 mass storage devices. Speed of FPGA emulation, though, is scaled down significantly because of inherent limitation of FPGA emulation while speed of interface to real connectivity devices is required to be at-speed for compliance with connectivity specification standards. For this reason, scaling factors of speed are not uniform and, thus, measurement of performance is not accurate. This paper proposes a method to compensate errors due to the non-uniform scaling factors. In the proposed method, measurements of various parameters in FPGA emulation are applied to a high-accuracy estimation model that we created. Our method was applied to USB2.0, and the experimental result shows 4.1% of estimation error.
- Universal Serial Bus Specification, Revision 2.0. April, 2000.Google Scholar
- R. Anderson, M. Borowczak, and P. A. Wilsey. The use of device simulation in development of usb storage devices. In Simulation Symposium, 2008. ANSS 2008. 41st Annual, pages 220--226, 2008. Google ScholarDigital Library
- H. Chen, Z. Liu, Z. Chen, and Z. Yuan. Estimating tcp throughput: A neural network approach. In Proceedings of the 6th World Congress on Intelligent Control and Automation, pages 2850--2854, June 2006.Google Scholar
- J. Corbet, A. Rubini, and G. Kroah-Hartman. Linux Device Drivers, Third Edition. O'Reilly Media, Inc., 2005. Google ScholarDigital Library
- U. I. Forum. Universal Serial Bus Mass Storage Class, Bulk-Only Transport Specification. 1999.Google Scholar
- J. Garney. An analysis of throughput characteristics of universal serial bus. Media and Interconnect Technology, Intel Architecture Labs, December 1996.Google Scholar
- C.-Y. Huang, T.-W. Kuo, and A.-C. Pang. Qos support for usb2.0 periodic and sporadic device requests. In Real-Time Systems Symposium, 2004. Proceedings. 25th IEEE International, pages 395--404, 2004. Google ScholarDigital Library
- J.-H. Hwang and C. Yoo. Formula-based tcp throughput prediction with available bandwidth. IEEE Communication Letters, 14(4):363--365, April 2010. Google ScholarDigital Library
- M. Inc. and D. Anderson. Universal Serial Bus System Architecture, 2nd Edition. Addison-Wesley Developer's Press, Reading, Massachusetts, 2001. Google ScholarDigital Library
- Intel. Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0. March, 2002.Google Scholar
- P. V. Knudsen and J. Madsen. Integrating communication protocol selection with hardware/software codesign. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(8):1077--1095, August 1999. Google ScholarDigital Library
- M. Opdenacker. Linux usb drivers. In http://free-electrons.com/doc/linux-usb.pdf. Free Electronics, September 2009.Google Scholar
- L. Organization. The linux-usb host side api. In http://www.kernel.org/doc/htmldocs/usb.html.Google Scholar
- R. Prasad, C. Dovrolis, M. Murray, and K. Claffy. Bandwidth estimation: Metrics, measurement techniques, and tools. Network, IEEE, 17(6):27--35, December 2003. Google ScholarDigital Library
- A. Rastogi, M. Balakrishnan, and A. Kumar. Integrating communication cost estimation in embedded systems design: A pci case study. In VLSI Design, 2001. Fourteenth International Conference on, pages 23--28, 2001. Google ScholarDigital Library
- ST-Ericsson. Usb throughput optimization, application notes. October 2009.Google Scholar
Recommendations
A High-Throughput Distributed Shared-Buffer NoC Router
Microarchitectural configurations of buffers in routers have a significant impact on the overall performance of an on-chip network (NoC). This buffering can be at the inputs or the outputs of a router, corresponding to an input-buffered router (IBR) or ...
FPGA implementation of AES algorithm for high throughput using folded parallel architecture
This paper presents high throughput architecture for the hardware implementation of Advanced Encryption Standard algorithm. Advanced Encryption Standard is the industry standard crypto algorithm for encryption and is used for protecting secret ...
Achieving High Throughput in High-Radix Switch
TRUSTCOM '11: Proceedings of the 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and CommunicationsCurrent research and trends reveals that high-radix switches can remarkably lower down the network diameter and switch count of interconnection network in high performance computers, and it is much valuable in saving packet latency, cost and power ...
Comments