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Design sensitivity of single event transients in scaled logic circuits

Published: 05 June 2011 Publication History

Abstract

Single Event Transients (SET) in digital logic pose an ever increasing reliability challenge as device dimensions shrink in modern technologies. Projection of SET sensitivity with scaling is essential to assess the logic failure and error probability in modern technology generations. This paper discusses the effects of device scaling from 45nm to 12nm processes and circuit parameter tuning on SETs. The failure due to particle strikes i.e., Single Event upsets (SEU) as well as its behavior with process variations and reliability mechanisms such as NBTI is evaluated in this work. The critical supply voltage required to avoid SET propagation with circuit parameters is investigated. This work also proposes a probability model which examines the propagation of SET at any node to the output of a circuit. The proposed methodology can be extended to any complex digital circuit to investigate its vulnerability to SET.

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      cover image ACM Conferences
      DAC '11: Proceedings of the 48th Design Automation Conference
      June 2011
      1055 pages
      ISBN:9781450306362
      DOI:10.1145/2024724
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      Published: 05 June 2011

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      Author Tags

      1. critical voltage
      2. double exponential current pulse
      3. failure probability
      4. single event transients

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      • (2024)Special Session: Overcoming Transient Faults and Aging Effects in Digital Computing-in-Memory Architectures: Detection, Tolerance, and Mitigation Strategies2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT63277.2024.10753529(1-6)Online publication date: 8-Oct-2024
      • (2023)Improving SET Fault Resilience by Exploiting Buffered DMR MicroarchitectureProceedings of SIE 202210.1007/978-3-031-26066-7_36(233-238)Online publication date: 28-Feb-2023
      • (2020)Topical Focus of Political Campaigns and its Impact: Findings from Politicians' Hashtag Use during the 2019 Indian ElectionsProceedings of the ACM on Human-Computer Interaction10.1145/33928604:CSCW1(1-14)Online publication date: 29-May-2020
      • (2020)C-Reference: Improving 2D to 3D Object Pose Estimation Accuracy via Crowdsourced Joint Object EstimationProceedings of the ACM on Human-Computer Interaction10.1145/33928584:CSCW1(1-28)Online publication date: 29-May-2020
      • (2020)Joint Effects of Aging and Process Variations on Soft Error Rate of Nano-Scale Digital CircuitsJournal of Circuits, Systems and Computers10.1142/S021812662150012230:01(2150012)Online publication date: 21-Jul-2020
      • (2019)Fine-Grained Hardware Mitigation for Multiple Long-Duration Transients on VLIW Function Units2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8714899(976-979)Online publication date: Mar-2019
      • (2017)Accelerated Soft-Error-Rate (SER) Estimation for Combinational and Sequential CircuitsACM Transactions on Design Automation of Electronic Systems10.1145/303549622:3(1-21)Online publication date: 25-May-2017
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      • (2016)Accelerating soft-error-rate (SER) estimation in the presence of single event transientsProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897976(1-6)Online publication date: 5-Jun-2016
      • (2016)Joint Soft-Error-Rate (SER) Estimation for Combinational Logic and Sequential Elements2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2016.28(737-742)Online publication date: Jul-2016
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