Andrew Zukoski
ABSTRACT
Double-gate carbon nanotube field-effect transistors (DG-CNT-FETs) can be controlled in the field to be either n-type or p-type through an extra polarity gate. This results in an embedded XOR behavior, which has inspired several novel circuit designs and architectures. This work makes the following contributions. First, we propose an accurate and efficient semi-classical modeling approach to realize the first SPICE-compatible model for circuit design and optimization of DG-CNTFETs. Second, we design and optimize universal logic modules (ULMs) in two circuit styles based on DG-CNTFETs. The proposed ULMs can leverage the full potential of the embedded XOR through the FPGA-centric lookup table optimization flow. Further, we demonstrate that DG-CNTFET ULMs in the double pass-transistor logic style, which inherently produces dual-rail outputs with balanced delay, are faster than DG-CNTFET circuits in the conventional single-rail static logic style that relies on explicit input inversion. On average across 12 benchmarks, the proposed dual-rail ULMs outperform the best DG-CNTFET fabrics based on tiling patterns by 37%, 12%, and 33% in area, delay, and total power, respectively.
- P. Avouris, Z. Chen, and V. Perebeinos, "Carbon-based electronics," Nature Nan-otechnology, vol. 2, pp. 605--615, 2007.Google Scholar
Cross Ref
- S. Heinze et al., "Carbon nanotubes as Schottky barrier transistors," Phys. Rev. Lett., vol. 89, p. 106801, 2002.Google ScholarCross Ref
- A. Javey et al., "Ballistic carbon nanotube field-effect transistors," Nature, vol. 424, pp. 654--657, 2003.Google ScholarCross Ref
- Y. Lin et al., "Ambipolar-to-unipolar conversion of carbon nanotube transistors by gate structure engineering," Nano Letters, vol. 4, pp. 947--950, 2004.Google ScholarCross Ref
- I. O'Connor et al., "CNTFET modeling and reconfigurable logic-circuit design," IEEE Trans. on Circuits and Systems I, vol. 54, pp. 2365--2379, 2007.Google ScholarCross Ref
- J. Liu et al., "Novel CNTFET-based reconfigurable logic gate design," in Proc. Design Automation Conference, pp. 276--277, 2007. Google ScholarDigital Library
- M. H. B. Jamaa et al., "Programmable logic circuits based on ambipolar CN-FET," in Proc. Design Automation Conference, pp. 339--340, 2008. Google ScholarDigital Library
- M. H. B. Jamaa et al., "Logic circuits with ambipolar CNTFETs: Novel opportunities for multi-level logic synthesis," in Proc. Design Automation and Test in Europe, pp. 622--627, 2009. Google ScholarDigital Library
- D. Marchi et al., "Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications," in Proc. Intl. Symposium on Nanoscale Architectures, pp. 65--70, 2010. Google ScholarDigital Library
- K. Jabeur et al., "Reducing transistor count in clocked standard cells with am-bipolar double-gate FETs," in Proc. Intl. Symposium on Nanoscale Architectures, pp. 47--52, 2010. Google ScholarDigital Library
- G. Fiori and G. Iannaccone, "NanoTCAD ViDES," 2008. DOI: 10254/nanohubr5116.3.Google Scholar
- M. Suzuki et al., "A 1.5ns 32--b CMOS ALU in double pass-transistor logic," Journal of Solid State Circuits, vol. 28, pp. 1145--1151, 1993.Google ScholarCross Ref
- J. Guo et al., "A numerical study of scaling issues for Schottky-barrier carbon nanotube transistors," IEEE Trans. on Electron Devices, vol. 51, pp. 172--177, 2004.Google ScholarCross Ref
- Y.-M. Lin et al., "High-performance carbon nanotube field-effect transistor with tunable polarities," IEEE Trans. Nanotechnology, vol. 4, pp. 481--489, 2005. Google ScholarDigital Library
- J. Deng and H. Wong, "A compact SPICE model for carbon-manotube field-effect transistors including nonidealities and its application --- Part I: Model of the intrinsic channel region," IEEE Trans. on Electron Devices, vol. 54, pp. 3186--3194, Dec. 2007.Google ScholarCross Ref
- A. Balijepalli et al., "Compact modeling of carbon nanotube transistor for early stage process-design exploration," in Proc. Intl. Symposium Low Power Electronics and Design, pp. 2--7, 2007. Google ScholarDigital Library
- A. Hazeghi et al., "Schottky-barrier carbon nanotube field-effect transistor modeling," IEEE Trans. on Electron Devices, vol. 54, no. 3, pp. 439--445, 2007.Google ScholarCross Ref
- X. Yang and K. Mohanram, "Modeling and performance investigation of the double-gate carbon nanotube transistor," IEEE Electron Device Lett., vol. 32, pp. 231--233, 2011.Google ScholarCross Ref
- Y. Tsividis, Operation and modeling of the MOS transistors. WCB/McGraw-Hill, 1999.Google Scholar
- N. Patil et al., "Circuit-level performance benchmarking and scalability analysis of carbon nanotube transistor circuits," IEEE Trans. Nanotechnology, vol. 8, pp. 37--45, 2009. Google ScholarDigital Library
- N. Song and M. A. Perkowski, "Exorcism-mv-2: Minimization of exclusive sum of products expressions for multiple-balued input incompletely specified functions," in Proc. Intl. Symposium on Multiple-Valued Logic, pp. 132--137, 1993.Google ScholarCross Ref
- J. P. Hansen and M. Sekine, "Synthesis by spectral translation using Boolean decision diagrams," in Proc. Design Automation Conference, pp. 248--253, 1996. Google ScholarDigital Library
- A. Bernasconi et al., "Efficient minimization of fully testable 2-spp networks," in Proc. Design, Automation and Test in Europe, pp. 1--6, 2006. Google ScholarDigital Library
- D. C. Forslund, "The universal logic block (ULB) and its application to logic design," Annual Symposium on Switching and Automata Theory, pp. 236--250, 1966. Google ScholarDigital Library
- S. Yau and C. Tang, "Universal logic modules and their applications," IEEE Transactions on Computers, vol. C-19, no. 2, pp. 141--149, 1970. Google ScholarDigital Library
- C. Edwards, "A special class of Universal logic gate (ULG) and their evaluation under the walsh transform," Computers and Digital Techniques, vol. 44, pp. 49--59, 1979.Google Scholar
- X. Chen and X. Wu, "Derivation of universal logic modules, for n≥3, by algebraic means," Computers and Digital Techniques, vol. 128, pp. 205--211, 1981.Google ScholarCross Ref
- M. Hutter, "Designing universal logic modules," in Proc. Intl. Conference on Electronics, Circuits and Systems, pp. 709--712, 2002.Google ScholarCross Ref
- S. Hurst, D. Miller, and J. Muzio, Spectral Techniques in Digital Logic. Academic Press Inc. (London) Ltd., 1985. Google ScholarDigital Library
- A. D. Franklin et al., "Length scaling of carbon nanotube transistors," Nature Nanotechnology, vol. 5, pp. 858--862, 2010.Google ScholarCross Ref
- "ABC Logic synthesis tool." Please visit the URL http://www.eecs.berkeley.edu/~alanmi/abc/for further details.Google Scholar
Index Terms
- Universal logic modules based on double-gate carbon nanotube transistors
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