research-article

A helper thread based dynamic cache partitioning scheme for multithreaded applications

Authors:

Mahmut Kandemir,

Taylan Yemliha,

Emre KultursayAuthors Info & Claims

DAC '11: Proceedings of the 48th Design Automation Conference

Pages 954 - 959

https://doi.org/10.1145/2024724.2024936

Published: 05 June 2011 Publication History

Abstract

Focusing on the problem of how to partition the cache space given to a multithreaded application across its threads, we show that different threads of a multithreaded application can have different cache space requirements, propose a fully automated, dynamic, intra-application cache partitioning scheme targeting emerging multicores with multilayer cache hierarchies, present a comprehensive experimental analysis of the proposed scheme, and show average improvements of 17.1% and 18.6% in SPECOMP and PARSEC suites.

References

[1]

V. Aslot et al. SPECOMP: A new benchmark suite for measuring parallel computer performance. In International Workshop on OpenMP Applications and Tools, 2001.

Digital Library

[2]

C. Bienia et al. The PARSEC benchmark suite: Characterization and architectural implications. In PACT, 2008.

Digital Library

[3]

D. Burger et al. Memory bandwidth limitations of future microprocessors. In ISCA, 1996.

Digital Library

[4]

D. Chandra et al. Predicting inter-thread cache contention on a chip multi-processor architecture. In HPCA, 2005.

Digital Library

[5]

J. Chang and G. S. Sohi. Cooperative cache partitioning for chip multiprocessors. In ICS, 2007.

Digital Library

[6]

Y. Ding et al. A helper thread based edp reduction scheme for adapting application execution in cmps. In IPDPS, 2008.

[7]

P. Duchesne and B. Remillard. Statistical Modeling and Analysis for Complex Data Problems. Springer, 2005.

Digital Library

[8]

F. Guo et al. A framework for providing quality of service in chip multi-processors. In MICRO, 2007.

Digital Library

[9]

J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 4th edition, 2007.

Digital Library

[10]

D. Kaseridis et al. A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large cmp systems. In HPCA, 2010.

[11]

S. Kim et al. Fair cache sharing and partitioning in a chip multiprocessor architecture. In PACT, 2004.

Digital Library

[12]

B. Ko et al. Scalable service differentiation in a shared storage cache. In ICDCS, 2003.

Digital Library

[13]

F. Liu et al. Understanding how off-chip memory bandwidth partitioning in chip multiprocessors affects system performance. In HPCA, 2010.

[14]

P. Magnusson et al. Simics: A full system simulation platform. Computer, 35(2), Feb 2002.

Digital Library

[15]

M. M. K. Martin et al. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. SIGARCH Comput. Archit. News, 33(4), 2005.

Digital Library

[16]

S. P. Muralidhara et al. Intra-application shared cache partitioning for multithreaded applications. In PPoPP, 2010.

Digital Library

[17]

M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In MICRO, 2006.

Digital Library

[18]

N. Rafique et al. Architectural support for operating system-driven CMP cache management. In PACT, 2006.

Digital Library

[19]

A. Snavely and D. M. Tullsen. Symbiotic job scheduling for a simultaneous multithreaded processor. In ASPLOS, 2000.

Digital Library

[20]

G. E. Suh et al. Dynamic partitioning of shared cache memory. J. Supercomput., 28(1), 2004.

Digital Library

Cited By

Mittal S(2017)A Survey of Techniques for Cache Partitioning in Multicore ProcessorsACM Computing Surveys10.1145/306239450:2(1-39)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3062394
Parihar RBrock JDing CHuang M(2016)Hardware support for protective and collaborative cache sharingACM SIGPLAN Notices10.1145/3241624.292670551:11(24-35)Online publication date: 14-Jun-2016
https://dl.acm.org/doi/10.1145/3241624.2926705
Parihar RBrock JDing CHuang MFlood CZhang Z(2016)Hardware support for protective and collaborative cache sharingProceedings of the 2016 ACM SIGPLAN International Symposium on Memory Management10.1145/2926697.2926705(24-35)Online publication date: 14-Jun-2016
https://dl.acm.org/doi/10.1145/2926697.2926705
Show More Cited By

Index Terms

A helper thread based dynamic cache partitioning scheme for multithreaded applications
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Information & Contributors

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Published In

cover image ACM Conferences

DAC '11: Proceedings of the 48th Design Automation Conference

June 2011

1055 pages

ISBN:9781450306362

DOI:10.1145/2024724

General Chair:
Leon Stok
IBM Corp., Hopewell Jct., NY
,
Program Chairs:
Nikil Dutt
Univ. of California, Irvine, CA
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE Council on Electronic Design Automation (CEDA)

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2011

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DAC '11

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EDAC
SIGDA

DAC '11: The 48th Annual Design Automation Conference 2011

June 5 - 10, 2011

California, San Diego

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

Sponsor:
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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Citations

Cited By

Mittal S(2017)A Survey of Techniques for Cache Partitioning in Multicore ProcessorsACM Computing Surveys10.1145/306239450:2(1-39)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3062394
Parihar RBrock JDing CHuang M(2016)Hardware support for protective and collaborative cache sharingACM SIGPLAN Notices10.1145/3241624.292670551:11(24-35)Online publication date: 14-Jun-2016
https://dl.acm.org/doi/10.1145/3241624.2926705
Parihar RBrock JDing CHuang MFlood CZhang Z(2016)Hardware support for protective and collaborative cache sharingProceedings of the 2016 ACM SIGPLAN International Symposium on Memory Management10.1145/2926697.2926705(24-35)Online publication date: 14-Jun-2016
https://dl.acm.org/doi/10.1145/2926697.2926705
Booth JKotra JZhao HKandemir MRaghavan P(2015)Phase Detection with Hidden Markov Models for DVFS on Many-Core Processors2015 IEEE 35th International Conference on Distributed Computing Systems10.1109/ICDCS.2015.27(185-195)Online publication date: Jun-2015
https://doi.org/10.1109/ICDCS.2015.27
Sironi FSciuto DSantambrogio M(2014)A performance-aware quality of service-driven scheduler for multicore processorsACM SIGBED Review10.1145/2597457.259746411:1(50-55)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1145/2597457.2597464
Kozhikkottu VPan APai VDey SRaghunathan A(2014)Variation Aware Cache Partitioning for Multithreaded ProgramsProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593240(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593240
Scolari ASironi FSciuto DSantambrogio M(2014)A Survey on Recent Hardware and Software-Level Cache Management TechniquesProceedings of the 2014 IEEE International Symposium on Parallel and Distributed Processing with Applications10.1109/ISPA.2014.41(242-247)Online publication date: 26-Aug-2014
https://dl.acm.org/doi/10.1109/ISPA.2014.41
Kozhikkottu VPan APai VDey SRaghunathan A(2014)Variation aware cache partitioning for multithreaded programs2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)10.1109/DAC.2014.6881526(1-6)Online publication date: Jun-2014
https://doi.org/10.1109/DAC.2014.6881526
Lai PFan R(2013)Makespan-Optimal Cache PartitioningProceedings of the 2013 IEEE 21st International Symposium on Modelling, Analysis & Simulation of Computer and Telecommunication Systems10.1109/MASCOTS.2013.28(202-211)Online publication date: 14-Aug-2013
https://dl.acm.org/doi/10.1109/MASCOTS.2013.28
Youssef AMansour MKhanna RKeshavamurthy ALe CGanguli M(2013)Autonomic tool for optimal cache-sharing using evolutionary techniques2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)10.1109/ICEAC.2013.6737658(169-174)Online publication date: Dec-2013
https://doi.org/10.1109/ICEAC.2013.6737658
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