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Architecting processors to allow voltage/reliability tradeoffs

Published: 09 October 2011 Publication History

Abstract

Escalating variations in modern CMOS designs have become a threat to Moore's law. While previous works have proposed techniques for tolerating variations by trading reliability for reduced voltage (energy) [10], the benefits of such techniques are limited, because voltage/reliability tradeoffs in conventional processors often introduce more errors than can be gainfully tolerated [14]. Recent work has proposed circuit and design-level optimizations [14, 15]that manipulate the error rate behavior of a design to increase the potential for energy savings from voltage/reliability tradeoffs. In this paper, we investigate whether architectural optimizations can also manipulate error rate behavior to significantly increase the energy savings from voltage/reliability tradeoffs. To this end, we demonstrate how error rate behavior indeed depends on processor architecture, and that architectural optimizations can be used to manipulate the error rate behavior of a processor. We show that architectural optimizations can significantly enhance voltage/reliability tradeoffs, achieving up to 29% additional energy savings for processors that employ Razor-based error resilience.

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cover image ACM Conferences
CASES '11: Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
October 2011
250 pages
ISBN:9781450307130
DOI:10.1145/2038698
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 09 October 2011

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Author Tags

  1. energy efficiency
  2. error resilience
  3. microarchitecture
  4. timing speculation

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ESWeek '11
ESWeek '11: Seventh Embedded Systems Week
October 9 - 14, 2011
Taipei, Taiwan

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Overall Acceptance Rate 52 of 230 submissions, 23%

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  • (2019)MinotaurProceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3297858.3304050(1087-1103)Online publication date: 4-Apr-2019
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  • (2016)Approxilyzer: Towards a systematic framework for instruction-level approximate computing and its application to hardware resiliency2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO.2016.7783745(1-14)Online publication date: Oct-2016
  • (2015)Overcoming Computational Errors in Sensing Platforms Through Embedded Machine-Learning KernelsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.234215323:8(1459-1470)Online publication date: 1-Aug-2015
  • (2014)Timing analysis of erroneous systemsProceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis10.1145/2656075.2656101(1-10)Online publication date: 12-Oct-2014
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