research-article

A design methodology to implement memory accesses in high-level synthesis

Authors:

Christian Pilato,

Fabrizio Ferrandi,

Donatella SciutoAuthors Info & Claims

CODES+ISSS '11: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 49 - 58

https://doi.org/10.1145/2039370.2039381

Published: 09 October 2011 Publication History

Abstract

Nowadays, the memory synthesis is becoming the main bottleneck for the generation of efficient hardware accelerators. This paper presents a design methodology to efficiently and automatically implement memory accesses in High-Level Synthesis. In particular, the approach starts from a behavioral specification (in pure C language) and a set of design constraints, such as the memory addresses where some of the data are stored.

The methodology classifies which variables can be internally or externally allocated to the different modules to generate the proper architecture, fully supporting a wide range of C constructs, such as pointer arithmetic, function calls and array accesses. Moreover it allows to parallelize the accesses when the memory address is known at compile time, resulting in an efficient execution of the specification.

References

[1]

GCC - GNU Compiler Collection. http://gcc.gnu.org.

[2]

Mentor ModelSim SE 6.6d User Guide. http://www.mentor.com.

[3]

Xilinx ISE Design Suite 12.3 User Guide. http://www.xilinx.com.

[4]

Xilinx Virtex-5 FPGA. http://www.xilinx.com/products/virtex5/.

[5]

A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, J. H. Anderson, S. Brown, and T. Czajkowski. LegUp: high-level synthesis for FPGA-based processor/accelerator systems. In Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays, FPGA '11, pages 33--36, New York, NY, USA, 2011. ACM.

Digital Library

[6]

G. De Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.

Digital Library

[7]

S. Gupta, N. Dutt, R. Gupta, and A. Nicolau. Spark: a high-level synthesis framework for applying parallelizing compiler transformations. Proceedings of the 16th International Conference on VLSI Design, pages 461--466, 4--8 Jan. 2003.

Digital Library

[8]

Y. Hara, H. Tomiyama, S. Honda, and H. Takada. Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis. Journal of Information Processing, 17:242--254, 2009.

[9]

L. J. Hendren, C. Donawa, M. Emami, G. R. Gao, Justiani, and B. Sridharan. Designing the McCAT Compiler Based on a Family of Structured Intermediate Representations. In 5th International Workshop on Languages and Compilers for Parallel Computing, pages 406--420, 1993.

Digital Library

[10]

C. Huang, S. Ravi, A. Raghunathan, and N. Jha. Generation of distributed logic-memory architectures through high-level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(11):1694--1711, Nov. 2005.

Digital Library

[11]

H. Lange, T. Wink, and A. Koch. Marc ii: A parametrized speculative multi-ported memory subsystem for reconfigurable computers. In Proceedings of the conference on Design, automation and test in Europe, DATE '11, 2011.

[12]

M. Miranda, F. Catthoor, M. Janssen, and H. De Man. High-level address optimization and synthesis techniques for data-transfer-intensive applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(4):677--686, Dec 1998.

Digital Library

[13]

P. Panda, N. Dutt, and A. Nicolau. Exploiting off-chip memory access modes in high-level synthesis. In IEEE/ACM International Conference on Computer-Aided Design, pages 333--340, November 1997.

Digital Library

[14]

P. R. Panda, F. Catthoor, N. D. Dutt, K. Danckaert, E. Brockmeyer, C. Kulkarni, A. Vandercappelle, and P. G. Kjeldsberg. Data and memory optimization techniques for embedded systems. ACM Transactions on Design Automation of Electronic Systems, 6:149--206, April 2001.

Digital Library

[15]

P. R. Panda, N. D. Dutt, and A. Nicolau. Architectural exploration and optimization of local memory in embedded systems. In Proceedings of the 10th international symposium on System synthesis, ISSS '97, pages 90--97, Washington, DC, USA, 1997. IEEE Computer Society.

Digital Library

[16]

L. Semeria and G. De Micheli. Resolution, optimization, and encoding of pointer variables for the behavioral synthesis from C. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(2):213--233, February 2001.

Digital Library

[17]

J. Zhu and D. D. Gajski. A unified formal model of ISA and FSMD. In Proceedings of the seventh international workshop on Hardware/software codesign, CODES '99, pages 121--125, New York, NY, USA, 1999. ACM.

Digital Library

Cited By

Pilato CSoldavini S(2024)Accelerator Design with High-Level SynthesisHandbook of Computer Architecture10.1007/978-981-97-9314-3_19(841-873)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-981-97-9314-3_19
Collini LTan BPilato CKarri RMitra TYoung EXiong J(2022)Reconfigurable Logic for Hardware IP ProtectionProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3561117(1-7)Online publication date: 30-Oct-2022
https://dl.acm.org/doi/10.1145/3508352.3561117
Ramanathan NConstantinides GWickerson J(2022)A Case for Precise, Fine-Grained Pointer Synthesis in High-Level SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/349143027:4(1-26)Online publication date: 8-Mar-2022
https://dl.acm.org/doi/10.1145/3491430
Show More Cited By

Index Terms

A design methodology to implement memory accesses in high-level synthesis
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

Recommendations

System-level memory optimization for high-level synthesis of component-based SoCs
CODES '14: Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis

The design of specialized accelerators is essential to the success of many modern Systems-on-Chip. Electronic system-level design methodologies and high-level synthesis tools are critical for the efficient design and optimization of an accelerator. ...
System-level memory optimization for high-level synthesis of component-based SoCs
CODES '14: Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis

The design of specialized accelerators is essential to the success of many modern Systems-on-Chip. Electronic system-level design methodologies and high-level synthesis tools are critical for the efficient design and optimization of an accelerator. ...
Layout-driven RTL binding techniques for high-level synthesis
ISSS '96: Proceedings of the 9th international symposium on System synthesis

The importance of effective and efficient accounting of layout effects is well-established in high-level synthesis (HLS), since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics. This ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

CODES+ISSS '11: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

October 2011

402 pages

ISBN:9781450307154

DOI:10.1145/2039370

Program Chairs:
Robert P. Dick
University of Michigan
,
Jan Madsen
Technical University of Denmark

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 09 October 2011

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ESWeek '11

Sponsor:

ESWeek '11: Seventh Embedded Systems Week

October 9 - 14, 2011

Taipei, Taiwan

Acceptance Rates

Overall Acceptance Rate 280 of 864 submissions, 32%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

18
Total Citations
View Citations
228
Total Downloads

Downloads (Last 12 months)7
Downloads (Last 6 weeks)0

Reflects downloads up to 05 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Pilato CSoldavini S(2024)Accelerator Design with High-Level SynthesisHandbook of Computer Architecture10.1007/978-981-97-9314-3_19(841-873)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-981-97-9314-3_19
Collini LTan BPilato CKarri RMitra TYoung EXiong J(2022)Reconfigurable Logic for Hardware IP ProtectionProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3561117(1-7)Online publication date: 30-Oct-2022
https://dl.acm.org/doi/10.1145/3508352.3561117
Ramanathan NConstantinides GWickerson J(2022)A Case for Precise, Fine-Grained Pointer Synthesis in High-Level SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/349143027:4(1-26)Online publication date: 8-Mar-2022
https://dl.acm.org/doi/10.1145/3491430
Pilato CSoldavini S(2022)Accelerator Design with High-Level SynthesisHandbook of Computer Architecture10.1007/978-981-15-6401-7_19-1(1-33)Online publication date: 27-Jan-2022
https://doi.org/10.1007/978-981-15-6401-7_19-1
Pilato CWu KGarg SKarri RRegazzoni F(2018)TaintHLS: High-Level Synthesis For Dynamic Information Flow TrackingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.2834421(1-1)Online publication date: 2018
https://doi.org/10.1109/TCAD.2018.2834421
Pilato CGarg SWu KKarri RRegazzoni F(2018)Securing Hardware Accelerators: A New Challenge for High-Level SynthesisIEEE Embedded Systems Letters10.1109/LES.2017.277480010:3(77-80)Online publication date: Sep-2018
https://doi.org/10.1109/LES.2017.2774800
Kechiche LTouil LOuni B(2017)SOPC for real time multi-video treatments with QoS requirements2017 International Conference on Engineering & MIS (ICEMIS)10.1109/ICEMIS.2017.8273096(1-7)Online publication date: May-2017
https://doi.org/10.1109/ICEMIS.2017.8273096
Nane RSima VPilato CChoi JFort BCanis AChen YHsiao HBrown SFerrandi FAnderson JBertels K(2016)A Survey and Evaluation of FPGA High-Level Synthesis ToolsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.251367335:10(1591-1604)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1109/TCAD.2015.2513673
Ravi SJoseph M(2016)Open source HLS tools: A stepping stone for modern electronic CAD2016 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)10.1109/ICCIC.2016.7919615(1-8)Online publication date: Dec-2016
https://doi.org/10.1109/ICCIC.2016.7919615
Fezzardi PFerrandi F(2016)Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers2016 26th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2016.7577369(1-9)Online publication date: Aug-2016
https://doi.org/10.1109/FPL.2016.7577369
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten