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Modeling and analysis of micro-ring based silicon photonic interconnect for embedded systems

Published: 09 October 2011 Publication History

Abstract

Recent advances in silicon photonic device and fabrication technologies make silicon photonic interconnect a promising communication fabric to address the inter-core and inter-die interconnect challenges for future embedded many-core processors. Informed design decisions in silicon photonic interconnection require optimization of performance, power efficiency, and reliability for different application scenarios. Optimizing these network and system metrics require understanding of silicon photonics device characteristics. However, existing design space exploration methodologies rely on time-consuming electromagnetic simulations or measurement of fabricated devices. In this paper, we introduce analytical models of devices, explore their design spaces, and apply them to different applications. The analytical models consist of parametrized transfer-matrices, with parameters categorized as fabrication-induced parameters and design parameters. Fabrication-induced parameters can be calibrated against measurements of fabricated devices to achieve high accuracy, whereas design parameters help in extrapolating the device characteristics. We develop and calibrate analytical models of widely used passive and doped micro-ring resonators. Three case studies of silicon photonic interconnects are discussed to represent different embedded applications and quantify the design trade-offs including performance requirements, power efficiency, and reliability constraints from the network system level.

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  • (2020)A Cross-Layer Optimization Framework for Integrated Optical Switches in Data CentersIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.289479239:3(640-653)Online publication date: Mar-2020
  • (2016)A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip InterconnectsProceedings of the 18th System Level Interconnect Prediction Workshop10.1145/2947357.2947362(1-8)Online publication date: 4-Jun-2016
  • (2016)Design of a High-Performance CDMA-Based Broadcast-Free Photonic Multi-Core Network on ChipACM Transactions on Embedded Computing Systems10.1145/283930115:1(1-30)Online publication date: 13-Jan-2016
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    cover image ACM Conferences
    CODES+ISSS '11: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
    October 2011
    402 pages
    ISBN:9781450307154
    DOI:10.1145/2039370
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 09 October 2011

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    Author Tags

    1. micro-rings
    2. optical interconnects
    3. silicon photonics

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    • Research-article

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    ESWeek '11
    ESWeek '11: Seventh Embedded Systems Week
    October 9 - 14, 2011
    Taipei, Taiwan

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    Cited By

    View all
    • (2020)A Cross-Layer Optimization Framework for Integrated Optical Switches in Data CentersIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.289479239:3(640-653)Online publication date: Mar-2020
    • (2016)A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip InterconnectsProceedings of the 18th System Level Interconnect Prediction Workshop10.1145/2947357.2947362(1-8)Online publication date: 4-Jun-2016
    • (2016)Design of a High-Performance CDMA-Based Broadcast-Free Photonic Multi-Core Network on ChipACM Transactions on Embedded Computing Systems10.1145/283930115:1(1-30)Online publication date: 13-Jan-2016
    • (2015)Compact modeling and system implications of microring modulators in nanophotonic interconnects2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)10.1109/SLIP.2015.7171708(1-6)Online publication date: 6-Jun-2015
    • (2014)Reliability-Aware Design Flow for Silicon Photonics On-Chip InterconnectIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.227838322:8(1763-1776)Online publication date: Aug-2014
    • (2013)Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-ChipIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.222057321:10(1823-1836)Online publication date: 1-Oct-2013
    • (2012)Design of an NoC with on-chip photonic interconnects using adaptive CDMA links2012 IEEE International SOC Conference10.1109/SOCC.2012.6398331(352-357)Online publication date: Sep-2012

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