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Dominator homomorphism based code matching for source-level simulation of embedded software

Published: 09 October 2011 Publication History

Abstract

Relating optimized binary code and the source-level statements from which it was created can be challenging if an optimizing compiler was used to create the machine code. Moreover, this relation is crucial if a compiler-optimized program must be debugged or results from a low-level analysis need to be mapped to the source code to perform manual optimizations. Existing approaches for the debugging of optimized code usually require pervasive changes in the compiler and hence are not available for all architectures. Methods for analyzing non-functional properties of software components in complex systems (i.e. execution time and power consumption) often have similar constraints, if compiler optimizations are supported at all.
This paper proposes two novel concepts to overcome these issues. To precisely relate source-level statements with the respective compiler-generated machine code, a method to reconstruct and disambiguate debug information is presented. Based on this information, an instrumentation technique is introduced which allows accurately simulating the execution of optimized binary code at the source code level. Experimental results show that by using this technique, arbitrary low-level properties of software components can be evaluated in a fast and accurate manner without running the software on the actual target hardware.

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Cited By

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  • (2022)Accurate LLVM IR to Binary CFGs Mapping for Simulation of Optimized Embedded SoftwareEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-031-04580-6_1(3-15)Online publication date: 27-Apr-2022
  • (2020)A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCsInternational Journal of Parallel Programming10.1007/s10766-020-00656-0Online publication date: 5-Mar-2020
  • (2019)WCET Analysis meets Virtual PrototypingProceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems10.1145/3323439.3323978(13-22)Online publication date: 27-May-2019
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      cover image ACM Conferences
      CODES+ISSS '11: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
      October 2011
      402 pages
      ISBN:9781450307154
      DOI:10.1145/2039370
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 09 October 2011

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      Author Tags

      1. simulation acceleration
      2. virtual prototypes

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      ESWeek '11
      ESWeek '11: Seventh Embedded Systems Week
      October 9 - 14, 2011
      Taipei, Taiwan

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      Overall Acceptance Rate 280 of 864 submissions, 32%

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      Cited By

      View all
      • (2022)Accurate LLVM IR to Binary CFGs Mapping for Simulation of Optimized Embedded SoftwareEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-031-04580-6_1(3-15)Online publication date: 27-Apr-2022
      • (2020)A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCsInternational Journal of Parallel Programming10.1007/s10766-020-00656-0Online publication date: 5-Mar-2020
      • (2019)WCET Analysis meets Virtual PrototypingProceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems10.1145/3323439.3323978(13-22)Online publication date: 27-May-2019
      • (2019) Systematic RISC-V based Firmware Design ⋆ 2019 Forum for Specification and Design Languages (FDL)10.1109/FDL.2019.8876945(1-8)Online publication date: Sep-2019
      • (2018)A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimationProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201717(452-457)Online publication date: 22-Jan-2018
      • (2018)A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimation2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297365(452-457)Online publication date: Jan-2018
      • (2017)Context-sensitive timing automata for fast source level simulationProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130497(512-517)Online publication date: 27-Mar-2017
      • (2017)Context-sensitive timing automata for fast source level simulationDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927042(512-517)Online publication date: Mar-2017
      • (2017)IR-level annotation strategy dealing with aggressive loop optimizations for performance estimation in native simulationProceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion10.1145/3125502.3125550(1-2)Online publication date: 15-Oct-2017
      • (2017)Timing Models for Fast Embedded Software Performance AnalysisHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_22-2(1-28)Online publication date: 18-Apr-2017
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