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Reliability-Driven Power/Ground Routing for Analog ICs

Published: 01 January 2012 Publication History

Abstract

Electromigration and voltage drop (IR-drop) are two major reliability issues in modern IC design. Electromigration gradually creates permanently open or short circuits due to excessive current densities; IR-drop causes insufficient power supply, thus degrading performance or even inducing functional errors because of nonzero wire resistance. Both types of failure can be triggered by insufficient wire widths. Although expanding the wire width alleviates electromigration and IR-drop, unlimited expansion not only increases the routing cost, but may also be infeasible due to the limited routing resource. In addition, electromigration and IR-drop manifest mainly in the power/ground (P/G) network. Therefore, taking wire widths into consideration is desirable to prevent electromigration and IR-drop at P/G routing. Unlike mature digital IC designs, P/G routing in analog ICs has not yet been well studied. In a conventional design, analog designers manually route P/G networks by implementing greedy strategies. However, the growing scale of analog ICs renders manual routing inefficient, and the greedy strategies may be ineffective when electromigration and IR-drop are considered. This study distances itself from conventional manual design and proposes an automatic analog P/G router that considers electromigration and IR-drops. First, employing transportation formulation, this article constructs an electromigration-aware rectilinear Steiner tree with the minimum routing cost. Second, without changing the solution quality, wires are bundled to release routing space for enhancing routability and relaxing congestion. A wire width extension method is subsequently adopted to reduce wire resistance for IR-drop safety. Compared with high-tech designs, the proposed approach achieves equally optimal solutions for electromigration avoidance, with superior efficiencies. Furthermore, via industrial design, experimental results also show the effectiveness and efficiency of the proposed algorithm for electromigration prevention and IR-drop reduction.

References

[1]
Black, J. 1969. Electromigration - A brief survey and some recent results. IEEE Trans. Electron Devices 16, 4, 338--347.
[2]
Cormen, T. H., Leiserson, C. E., Rivest, R. L., and Stein, C. 2009. Introduction to Algorithms 3rd Ed., MIT Press.
[3]
Dutta, R. and Marek-Sadowska, M. 1989. Automatic sizing of power/ground (p/g) networks in VLSI. In Proceedings of the IEEE/ACM Design Automation Conference (DAC’89). ACM, New York, 783--786.
[4]
Ho, J.-M., Vijayan, G., and Wong, C. K. 1990. New algorithms for the rectilinear steiner tree problem. IEEE Trans. Comput.-Aid. Des. Integrat. Circuits Syst. 9, 2, 185--193.
[5]
Jiang, I. H.-R., Chang, H.-Y., and Chang, C.-L. 2010. Optimal wiring topology for electromigration-avoidance considering multiple layers and obstacles. In Proceedings of the International Symposium on Physical Design (ISPD’10). ACM, New York, 177--184.
[6]
Lienig, J. 2006. Introduction to electromigration-aware physical design. In Proceedings of the International Symposium on Physical Design (ISPD’06). ACM, New York, 39--46.
[7]
Lienig, J. and Jerke, G. 2003. Current-driven wire planning for electromigration avoidance in analog circuits. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC’03). ACM, New York, 783--788.
[8]
Lin, C.-W., Chen, S.-Y., Li, C.-F., Chang, Y.-W., and Yang, C.-L. 2008. Obstacle-avoiding rectilinear Steiner tree construction based on spanning graphs. IEEE Trans. Comput.-Aid. Des. Integrat. Circuits Syst. 27, 4, 643--653.
[9]
McMurchie, L. and Ebeling, C. 1995. Pathfinder: A negotiation-based performance-driven router for FPGAs. In Proceedings of the ACM Symposium on Field-Programmable Gate Arrays (FPGA’95). ACM, New York, 111--117.
[10]
Pan, M. and Chu, C. 2006. A step to integrate global routing into placement. In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD’06). IEEE, Los Alamitos, CA, 464--471.
[11]
Russell, E. J. 1969. Extension of Dantzig’s algorithm to finding an initial near-optimal basis for the transportation problem. Oper. Res. 17, 1, 187--191.
[12]
Silva, J. M. S., Phillips, J. R., and Silveira, L. M. 2008. Efficient representation and analysis of power grids. In Proceedings of the Conference on Design, Automation, and Test in Europe (DATE’08). ACM, New York, 420-425.
[13]
Todri, A., Marek-Sadowska, M., and Chang, S.-C. 2007. Analysis and optimization of power-gated ICS with multiple power gating configurations. In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD’07). IEEE, Los Alamitos, CA, 783--790.
[14]
Winston, W. L. 2004. Operations Research Applications and Algorithms 4th Ed., Thomsom Brooks/Cole.
[15]
Yan, J.-T. and Chen, Z.-W. 2008. Electromigration-aware rectilinear Steiner tree construction for analog circuits. In Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS’08). IEEE, Los Alamitos, CA, 1692--1695.

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  • (2024)Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper)2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473859(679-685)Online publication date: 22-Jan-2024
  • (2022)CAD for Analog/Mixed‐Signal Integrated CircuitsAdvances in Semiconductor Technologies10.1002/9781119869610.ch3(43-60)Online publication date: 30-Sep-2022
  • (2020)Challenges and opportunities toward fully automated analog layout designJournal of Semiconductors10.1088/1674-4926/41/11/11140741:11(111407)Online publication date: 1-Nov-2020
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Published In

cover image ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems  Volume 17, Issue 1
January 2012
224 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/2071356
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 January 2012
Accepted: 01 August 2011
Revised: 01 July 2011
Received: 01 January 2011
Published in TODAES Volume 17, Issue 1

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Author Tags

  1. Analog
  2. IR-drop
  3. Steiner tree
  4. electromigration
  5. power/ground network
  6. routing

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View all
  • (2024)Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper)2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473859(679-685)Online publication date: 22-Jan-2024
  • (2022)CAD for Analog/Mixed‐Signal Integrated CircuitsAdvances in Semiconductor Technologies10.1002/9781119869610.ch3(43-60)Online publication date: 30-Sep-2022
  • (2020)Challenges and opportunities toward fully automated analog layout designJournal of Semiconductors10.1088/1674-4926/41/11/11140741:11(111407)Online publication date: 1-Nov-2020
  • (2019)IR-aware Power Net Routing for Multi-Voltage Mixed-Signal Design2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715166(72-77)Online publication date: Mar-2019
  • (2019)GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD45719.2019.8942164(1-8)Online publication date: Nov-2019
  • (2016)Recent research development and new challenges in analog layout synthesis2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2016.7428080(617-622)Online publication date: Jan-2016

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